| From c34151a742d84ae65db2088ea30495063f697fbe Mon Sep 17 00:00:00 2001 |
| From: Joerg Roedel <joerg.roedel@amd.com> |
| Date: Mon, 18 Apr 2011 15:45:45 +0200 |
| Subject: x86, gart: Set DISTLBWALKPRB bit always |
| |
| From: Joerg Roedel <joerg.roedel@amd.com> |
| |
| commit c34151a742d84ae65db2088ea30495063f697fbe upstream. |
| |
| The DISTLBWALKPRB bit must be set for the GART because the |
| gatt table is mapped UC. But the current code does not set |
| the bit at boot when the BIOS setup the aperture correctly. |
| Fix that by setting this bit when enabling the GART instead |
| of the other places. |
| |
| Cc: Borislav Petkov <borislav.petkov@amd.com> |
| Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> |
| Link: http://lkml.kernel.org/r/1303134346-5805-4-git-send-email-joerg.roedel@amd.com |
| Signed-off-by: H. Peter Anvin <hpa@zytor.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> |
| |
| --- |
| arch/x86/include/asm/gart.h | 4 ++-- |
| arch/x86/kernel/aperture_64.c | 2 +- |
| 2 files changed, 3 insertions(+), 3 deletions(-) |
| |
| --- a/arch/x86/include/asm/gart.h |
| +++ b/arch/x86/include/asm/gart.h |
| @@ -66,7 +66,7 @@ static inline void gart_set_size_and_ena |
| * Don't enable translation but enable GART IO and CPU accesses. |
| * Also, set DISTLBWALKPRB since GART tables memory is UC. |
| */ |
| - ctl = DISTLBWALKPRB | order << 1; |
| + ctl = order << 1; |
| |
| pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
| } |
| @@ -83,7 +83,7 @@ static inline void enable_gart_translati |
| |
| /* Enable GART translation for this hammer. */ |
| pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl); |
| - ctl |= GARTEN; |
| + ctl |= GARTEN | DISTLBWALKPRB; |
| ctl &= ~(DISGARTCPU | DISGARTIO); |
| pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl); |
| } |
| --- a/arch/x86/kernel/aperture_64.c |
| +++ b/arch/x86/kernel/aperture_64.c |
| @@ -500,7 +500,7 @@ out: |
| * Don't enable translation yet but enable GART IO and CPU |
| * accesses and set DISTLBWALKPRB since GART table memory is UC. |
| */ |
| - u32 ctl = DISTLBWALKPRB | aper_order << 1; |
| + u32 ctl = aper_order << 1; |
| |
| bus = amd_nb_bus_dev_ranges[i].bus; |
| dev_base = amd_nb_bus_dev_ranges[i].dev_base; |