| From b25f3e1c358434bf850220e04f28eebfc45eb634 Mon Sep 17 00:00:00 2001 |
| From: Taras Kondratiuk <taras.kondratiuk@linaro.org> |
| Date: Fri, 10 Jan 2014 01:27:08 +0100 |
| Subject: ARM: 7938/1: OMAP4/highbank: Flush L2 cache before disabling |
| |
| From: Taras Kondratiuk <taras.kondratiuk@linaro.org> |
| |
| commit b25f3e1c358434bf850220e04f28eebfc45eb634 upstream. |
| |
| Kexec disables outer cache before jumping to reboot code, but it doesn't |
| flush it explicitly. Flush is done implicitly inside of l2x0_disable(). |
| But some SoC's override default .disable handler and don't flush cache. |
| This may lead to a corrupted memory during Kexec reboot on these |
| platforms. |
| |
| This patch adds cache flush inside of OMAP4 and Highbank outer_cache.disable() |
| handlers to make it consistent with default l2x0_disable(). |
| |
| Acked-by: Rob Herring <rob.herring@calxeda.com> |
| Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> |
| Acked-by: Tony Lindgren <tony@atomide.com> |
| Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org> |
| Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
| Cc: Wang Nan <wangnan0@huawei.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/arm/mach-highbank/highbank.c | 1 + |
| arch/arm/mach-omap2/omap4-common.c | 1 + |
| 2 files changed, 2 insertions(+) |
| |
| --- a/arch/arm/mach-highbank/highbank.c |
| +++ b/arch/arm/mach-highbank/highbank.c |
| @@ -66,6 +66,7 @@ void highbank_set_cpu_jump(int cpu, void |
| |
| static void highbank_l2x0_disable(void) |
| { |
| + outer_flush_all(); |
| /* Disable PL310 L2 Cache controller */ |
| highbank_smc1(0x102, 0x0); |
| } |
| --- a/arch/arm/mach-omap2/omap4-common.c |
| +++ b/arch/arm/mach-omap2/omap4-common.c |
| @@ -163,6 +163,7 @@ void __iomem *omap4_get_l2cache_base(voi |
| |
| static void omap4_l2x0_disable(void) |
| { |
| + outer_flush_all(); |
| /* Disable PL310 L2 Cache controller */ |
| omap_smc1(0x102, 0x0); |
| } |