| From f66fab8e1cd6b3127ba4c5c0d11539fbe1de1e36 Mon Sep 17 00:00:00 2001 |
| From: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Date: Tue, 11 Feb 2014 19:52:06 +0200 |
| Subject: drm/i915: Prevent MI_DISPLAY_FLIP straddling two cachelines on IVB |
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| |
| From: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| |
| commit f66fab8e1cd6b3127ba4c5c0d11539fbe1de1e36 upstream. |
| |
| According to BSpec the entire MI_DISPLAY_FLIP packet must be contained |
| in a single cacheline. Make sure that happens. |
| |
| v2: Use intel_ring_begin_cacheline_safe() |
| v3: Use intel_ring_cacheline_align() (Chris) |
| |
| Cc: Bjoern C <lkml@call-home.ch> |
| Cc: Alexandru DAMIAN <alexandru.damian@intel.com> |
| Cc: Enrico Tagliavini <enrico.tagliavini@gmail.com> |
| Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74053 |
| Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++++ |
| 1 file changed, 14 insertions(+) |
| |
| --- a/drivers/gpu/drm/i915/intel_display.c |
| +++ b/drivers/gpu/drm/i915/intel_display.c |
| @@ -8335,6 +8335,20 @@ static int intel_gen7_queue_flip(struct |
| if (ring->id == RCS) |
| len += 6; |
| |
| + /* |
| + * BSpec MI_DISPLAY_FLIP for IVB: |
| + * "The full packet must be contained within the same cache line." |
| + * |
| + * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same |
| + * cacheline, if we ever start emitting more commands before |
| + * the MI_DISPLAY_FLIP we may need to first emit everything else, |
| + * then do the cacheline alignment, and finally emit the |
| + * MI_DISPLAY_FLIP. |
| + */ |
| + ret = intel_ring_cacheline_align(ring); |
| + if (ret) |
| + goto err_unpin; |
| + |
| ret = intel_ring_begin(ring, len); |
| if (ret) |
| goto err_unpin; |