| From a7f1c1e65b68e1e1ab70898528d5977ed68a0a7d Mon Sep 17 00:00:00 2001 |
| From: Ilia Mirkin <imirkin@alum.mit.edu> |
| Date: Thu, 13 Feb 2014 21:57:15 -0500 |
| Subject: drm/nv50/disp: use correct register to determine DP display bpp |
| |
| From: Ilia Mirkin <imirkin@alum.mit.edu> |
| |
| commit a7f1c1e65b68e1e1ab70898528d5977ed68a0a7d upstream. |
| |
| Commit 0a0afd282f ("drm/nv50-/disp: move DP link training to core and |
| train from supervisor") added code that uses the wrong register for |
| computing the display bpp, used for bandwidth calculation. Adjust to use |
| the same register as used by exec_clkcmp and nv50_disp_intr_unk20_2_dp. |
| |
| Reported-by: Torsten Wagner <torsten.wagner@gmail.com> |
| Reported-by: Michael Gulick <mgulick@mathworks.com> |
| Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67628 |
| Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu> |
| Signed-off-by: Ben Skeggs <bskeggs@redhat.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/gpu/drm/nouveau/core/engine/disp/nv50.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c |
| +++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c |
| @@ -1112,7 +1112,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_ |
| if (conf != ~0) { |
| if (outp.location == 0 && outp.type == DCB_OUTPUT_DP) { |
| u32 soff = (ffs(outp.or) - 1) * 0x08; |
| - u32 ctrl = nv_rd32(priv, 0x610798 + soff); |
| + u32 ctrl = nv_rd32(priv, 0x610794 + soff); |
| u32 datarate; |
| |
| switch ((ctrl & 0x000f0000) >> 16) { |
