| From 995ab5189d1d7264e79e665dfa032a19b3ac646e Mon Sep 17 00:00:00 2001 |
| From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| Date: Tue, 25 Nov 2014 18:43:15 +0100 |
| Subject: ARM: 8222/1: mvebu: enable strex backoff delay |
| |
| From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| |
| commit 995ab5189d1d7264e79e665dfa032a19b3ac646e upstream. |
| |
| Under extremely rare conditions, in an MPCore node consisting of at |
| least 3 CPUs, two CPUs trying to perform a STREX to data on the same |
| shared cache line can enter a livelock situation. |
| |
| This patch enables the HW mechanism that overcomes the bug. This fixes |
| the incorrect setup of the STREX backoff delay bit due to a wrong |
| description in the specification. |
| |
| Note that enabling the STREX backoff delay mechanism is done by |
| leaving the bit *cleared*, while the bit was currently being set by |
| the proc-v7.S code. |
| |
| [Thomas: adapt to latest mainline, slightly reword the commit log, add |
| stable markers.] |
| |
| Fixes: de4901933f6d ("arm: mm: Add support for PJ4B cpu and init routines") |
| |
| Signed-off-by: Nadav Haklai <nadavh@marvell.com> |
| Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
| Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> |
| Acked-by: Jason Cooper <jason@lakedaemon.net> |
| Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/arm/mm/proc-v7.S | 2 -- |
| 1 file changed, 2 deletions(-) |
| |
| --- a/arch/arm/mm/proc-v7.S |
| +++ b/arch/arm/mm/proc-v7.S |
| @@ -211,7 +211,6 @@ __v7_pj4b_setup: |
| /* Auxiliary Debug Modes Control 1 Register */ |
| #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */ |
| #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */ |
| -#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */ |
| #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */ |
| |
| /* Auxiliary Debug Modes Control 2 Register */ |
| @@ -234,7 +233,6 @@ __v7_pj4b_setup: |
| /* Auxiliary Debug Modes Control 1 Register */ |
| mrc p15, 1, r0, c15, c1, 1 |
| orr r0, r0, #PJ4B_CLEAN_LINE |
| - orr r0, r0, #PJ4B_BCK_OFF_STREX |
| orr r0, r0, #PJ4B_INTER_PARITY |
| bic r0, r0, #PJ4B_STATIC_BP |
| mcr p15, 1, r0, c15, c1, 1 |
