| From 8e66e134e20b936179ea1535dd4ed19ec4f99dba Mon Sep 17 00:00:00 2001 |
| From: Alex Deucher <alexander.deucher@amd.com> |
| Date: Wed, 15 Oct 2014 17:20:55 -0400 |
| Subject: drm/radeon: fix vm page table block size calculation |
| |
| From: Alex Deucher <alexander.deucher@amd.com> |
| |
| commit 8e66e134e20b936179ea1535dd4ed19ec4f99dba upstream. |
| |
| The page offset is 12 bits. For example if we have an |
| 8 GB VM, we'd need 33 bits. The number of bits needed |
| for PD + PT is 21 (33 - 12 or log2(8) + 18), not 20 |
| (log2(8) + 17). |
| |
| Noticed by Alexey during code review. |
| |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/gpu/drm/radeon/radeon_device.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/drivers/gpu/drm/radeon/radeon_device.c |
| +++ b/drivers/gpu/drm/radeon/radeon_device.c |
| @@ -1130,7 +1130,7 @@ static void radeon_check_arguments(struc |
| if (radeon_vm_block_size == -1) { |
| |
| /* Total bits covered by PD + PTs */ |
| - unsigned bits = ilog2(radeon_vm_size) + 17; |
| + unsigned bits = ilog2(radeon_vm_size) + 18; |
| |
| /* Make sure the PD is 4K in size up to 8GB address space. |
| Above that split equal between PD and PTs */ |
