| From aece118e487a744eafcdd0c77fe32b55ee2092a1 Mon Sep 17 00:00:00 2001 |
| From: Bryan O'Donoghue <pure.logic@nexus-software.ie> |
| Date: Tue, 7 Oct 2014 01:19:49 +0100 |
| Subject: x86: Add cpu_detect_cache_sizes to init_intel() add Quark legacy_cache() |
| |
| From: Bryan O'Donoghue <pure.logic@nexus-software.ie> |
| |
| commit aece118e487a744eafcdd0c77fe32b55ee2092a1 upstream. |
| |
| Intel processors which don't report cache information via cpuid(2) |
| or cpuid(4) need quirk code in the legacy_cache_size callback to |
| report this data. For Intel that callback is is intel_size_cache(). |
| |
| This patch enables calling of cpu_detect_cache_sizes() inside of |
| init_intel() and hence the calling of the legacy_cache callback in |
| intel_size_cache(). Adding this call will ensure that PIII Tualatin |
| currently in intel_size_cache() and Quark SoC X1000 being added to |
| intel_size_cache() in this patch will report their respective cache |
| sizes. |
| |
| This model of calling cpu_detect_cache_sizes() is consistent with |
| AMD/Via/Cirix/Transmeta and Centaur. |
| |
| Also added is a string to idenitfy the Quark as Quark SoC X1000 |
| giving better and more descriptive output via /proc/cpuinfo |
| |
| Adding cpu_detect_cache_sizes to init_intel() will enable calling |
| of intel_size_cache() on Intel processors which currently no code |
| can reach. Therefore this patch will also re-enable reporting |
| of PIII Tualatin cache size information as well as add |
| Quark SoC X1000 support. |
| |
| Comment text and cache flow logic suggested by Thomas Gleixner |
| |
| Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie> |
| Cc: davej@redhat.com |
| Cc: hmh@hmh.eng.br |
| Link: http://lkml.kernel.org/r/1412641189-12415-3-git-send-email-pure.logic@nexus-software.ie |
| Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
| Signed-off-by: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/x86/kernel/cpu/intel.c | 17 ++++++++++++++++- |
| 1 file changed, 16 insertions(+), 1 deletion(-) |
| |
| --- a/arch/x86/kernel/cpu/intel.c |
| +++ b/arch/x86/kernel/cpu/intel.c |
| @@ -397,6 +397,13 @@ static void init_intel(struct cpuinfo_x8 |
| } |
| |
| l2 = init_intel_cacheinfo(c); |
| + |
| + /* Detect legacy cache sizes if init_intel_cacheinfo did not */ |
| + if (l2 == 0) { |
| + cpu_detect_cache_sizes(c); |
| + l2 = c->x86_cache_size; |
| + } |
| + |
| if (c->cpuid_level > 9) { |
| unsigned eax = cpuid_eax(10); |
| /* Check for version and the number of counters */ |
| @@ -500,6 +507,13 @@ static unsigned int intel_size_cache(str |
| */ |
| if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) |
| size = 256; |
| + |
| + /* |
| + * Intel Quark SoC X1000 contains a 4-way set associative |
| + * 16K cache with a 16 byte cache line and 256 lines per tag |
| + */ |
| + if ((c->x86 == 5) && (c->x86_model == 9)) |
| + size = 16; |
| return size; |
| } |
| #endif |
| @@ -701,7 +715,8 @@ static const struct cpu_dev intel_cpu_de |
| [3] = "OverDrive PODP5V83", |
| [4] = "Pentium MMX", |
| [7] = "Mobile Pentium 75 - 200", |
| - [8] = "Mobile Pentium MMX" |
| + [8] = "Mobile Pentium MMX", |
| + [9] = "Quark SoC X1000", |
| } |
| }, |
| { .family = 6, .model_names = |