| From cdd781ab1906d039c2a93078385645d2d5af8491 Mon Sep 17 00:00:00 2001 |
| From: Sascha Hauer <s.hauer@pengutronix.de> |
| Date: Mon, 4 Jun 2012 14:58:07 +0200 |
| Subject: ARM i.MX53: Fix PLL4 base address |
| |
| From: Sascha Hauer <s.hauer@pengutronix.de> |
| |
| commit cdd781ab1906d039c2a93078385645d2d5af8491 upstream. |
| |
| MX53_DPLL4_BASE accidently returned the base address of PLL3. |
| Fix this. |
| |
| Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/arm/mach-imx/crm-regs-imx5.h | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/arch/arm/mach-imx/crm-regs-imx5.h |
| +++ b/arch/arm/mach-imx/crm-regs-imx5.h |
| @@ -23,7 +23,7 @@ |
| #define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR) |
| #define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR) |
| #define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) |
| -#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR) |
| +#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL4_BASE_ADDR) |
| |
| /* PLL Register Offsets */ |
| #define MXC_PLL_DP_CTL 0x00 |
