| From 26cb7b7b319acea0cc7011ebe2fc9ca8f2e4a687 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Sun, 16 May 2021 19:30:35 +0300 |
| Subject: clk: tegra: Ensure that PLLU configuration is applied properly |
| |
| From: Dmitry Osipenko <digetx@gmail.com> |
| |
| [ Upstream commit a7196048cd5168096c2c4f44a3939d7a6dcd06b9 ] |
| |
| The PLLU (USB) consists of the PLL configuration itself and configuration |
| of the PLLU outputs. The PLLU programming is inconsistent on T30 vs T114, |
| where T114 immediately bails out if PLLU is enabled and T30 re-enables |
| a potentially already enabled PLL (left after bootloader) and then fully |
| reprograms it, which could be unsafe to do. The correct way should be to |
| skip enabling of the PLL if it's already enabled and then apply |
| configuration to the outputs. This patch doesn't fix any known problems, |
| it's a minor improvement. |
| |
| Acked-by: Thierry Reding <treding@nvidia.com> |
| Signed-off-by: Dmitry Osipenko <digetx@gmail.com> |
| Signed-off-by: Thierry Reding <treding@nvidia.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/clk/tegra/clk-pll.c | 6 ++++-- |
| 1 file changed, 4 insertions(+), 2 deletions(-) |
| |
| diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c |
| index dc87866233b9..ed3b725ff102 100644 |
| --- a/drivers/clk/tegra/clk-pll.c |
| +++ b/drivers/clk/tegra/clk-pll.c |
| @@ -1091,7 +1091,8 @@ static int clk_pllu_enable(struct clk_hw *hw) |
| if (pll->lock) |
| spin_lock_irqsave(pll->lock, flags); |
| |
| - _clk_pll_enable(hw); |
| + if (!clk_pll_is_enabled(hw)) |
| + _clk_pll_enable(hw); |
| |
| ret = clk_pll_wait_for_lock(pll); |
| if (ret < 0) |
| @@ -1708,7 +1709,8 @@ static int clk_pllu_tegra114_enable(struct clk_hw *hw) |
| if (pll->lock) |
| spin_lock_irqsave(pll->lock, flags); |
| |
| - _clk_pll_enable(hw); |
| + if (!clk_pll_is_enabled(hw)) |
| + _clk_pll_enable(hw); |
| |
| ret = clk_pll_wait_for_lock(pll); |
| if (ret < 0) |
| -- |
| 2.30.2 |
| |