| From foo@baz Sun Jun 17 12:07:34 CEST 2018 |
| From: Sekhar Nori <nsekhar@ti.com> |
| Date: Fri, 11 May 2018 20:51:34 +0530 |
| Subject: ARM: davinci: dm646x: fix timer interrupt generation |
| |
| From: Sekhar Nori <nsekhar@ti.com> |
| |
| [ Upstream commit 73d4337ed9ceddef4b2f0e226634d5f985aa2d1c ] |
| |
| commit b38434145b34 ("ARM: davinci: irqs: Correct McASP1 TX interrupt |
| definition for DM646x") inadvertently removed priority setting for |
| timer0_12 (bottom half of timer0). This timer is used as clockevent. |
| |
| When INTPRIn register setting for an interrupt is left at 0, it is |
| mapped to FIQ by the AINTC causing the timer interrupt to not get |
| generated. |
| |
| Fix it by including an entry for timer0_12 in interrupt priority map |
| array. While at it, move the clockevent comment to the right place. |
| |
| Fixes: b38434145b34 ("ARM: davinci: irqs: Correct McASP1 TX interrupt definition for DM646x") |
| Signed-off-by: Sekhar Nori <nsekhar@ti.com> |
| Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/arm/mach-davinci/dm646x.c | 3 ++- |
| 1 file changed, 2 insertions(+), 1 deletion(-) |
| |
| --- a/arch/arm/mach-davinci/dm646x.c |
| +++ b/arch/arm/mach-davinci/dm646x.c |
| @@ -495,7 +495,8 @@ static u8 dm646x_default_priorities[DAVI |
| [IRQ_DM646X_MCASP0TXINT] = 7, |
| [IRQ_DM646X_MCASP0RXINT] = 7, |
| [IRQ_DM646X_RESERVED_3] = 7, |
| - [IRQ_DM646X_MCASP1TXINT] = 7, /* clockevent */ |
| + [IRQ_DM646X_MCASP1TXINT] = 7, |
| + [IRQ_TINT0_TINT12] = 7, /* clockevent */ |
| [IRQ_TINT0_TINT34] = 7, /* clocksource */ |
| [IRQ_TINT1_TINT12] = 7, /* DSP timer */ |
| [IRQ_TINT1_TINT34] = 7, /* system tick */ |
