| From foo@baz Sun Jun 17 12:07:34 CEST 2018 |
| From: David Gilhooley <dgilhooley@nvidia.com> |
| Date: Tue, 8 May 2018 15:49:42 -0700 |
| Subject: arm64: Add MIDR encoding for NVIDIA CPUs |
| |
| From: David Gilhooley <dgilhooley@nvidia.com> |
| |
| [ Upstream commit 1b06bd8dd95f7a19ab33fdf0f477c94950822ab3 ] |
| |
| This patch adds the MIDR encodings for NVIDIA as well as |
| the Denver and Carmel CPUs used in Tegra SoCs. |
| |
| Signed-off-by: David Gilhooley <dgilhooley@nvidia.com> |
| Signed-off-by: Will Deacon <will.deacon@arm.com> |
| Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/arm64/include/asm/cputype.h | 6 ++++++ |
| 1 file changed, 6 insertions(+) |
| |
| --- a/arch/arm64/include/asm/cputype.h |
| +++ b/arch/arm64/include/asm/cputype.h |
| @@ -75,6 +75,7 @@ |
| #define ARM_CPU_IMP_CAVIUM 0x43 |
| #define ARM_CPU_IMP_BRCM 0x42 |
| #define ARM_CPU_IMP_QCOM 0x51 |
| +#define ARM_CPU_IMP_NVIDIA 0x4E |
| |
| #define ARM_CPU_PART_AEM_V8 0xD0F |
| #define ARM_CPU_PART_FOUNDATION 0xD00 |
| @@ -98,6 +99,9 @@ |
| #define QCOM_CPU_PART_FALKOR 0xC00 |
| #define QCOM_CPU_PART_KRYO 0x200 |
| |
| +#define NVIDIA_CPU_PART_DENVER 0x003 |
| +#define NVIDIA_CPU_PART_CARMEL 0x004 |
| + |
| #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) |
| #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) |
| #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) |
| @@ -112,6 +116,8 @@ |
| #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) |
| #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) |
| #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO) |
| +#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) |
| +#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) |
| |
| #ifndef __ASSEMBLY__ |
| |
