| From foo@baz Sun Jun 17 12:07:33 CEST 2018 |
| From: Paolo Bonzini <pbonzini@redhat.com> |
| Date: Fri, 13 Apr 2018 11:38:35 +0200 |
| Subject: kvm: x86: move MSR_IA32_TSC handling to x86.c |
| |
| From: Paolo Bonzini <pbonzini@redhat.com> |
| |
| [ Upstream commit dd259935e4eec844dc3e5b8a7cd951cd658b4fb6 ] |
| |
| This is not specific to Intel/AMD anymore. The TSC offset is available |
| in vcpu->arch.tsc_offset. |
| |
| Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
| Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/x86/kvm/svm.c | 9 --------- |
| arch/x86/kvm/vmx.c | 20 -------------------- |
| arch/x86/kvm/x86.c | 6 ++++++ |
| 3 files changed, 6 insertions(+), 29 deletions(-) |
| |
| --- a/arch/x86/kvm/svm.c |
| +++ b/arch/x86/kvm/svm.c |
| @@ -3915,12 +3915,6 @@ static int svm_get_msr(struct kvm_vcpu * |
| struct vcpu_svm *svm = to_svm(vcpu); |
| |
| switch (msr_info->index) { |
| - case MSR_IA32_TSC: { |
| - msr_info->data = svm->vmcb->control.tsc_offset + |
| - kvm_scale_tsc(vcpu, rdtsc()); |
| - |
| - break; |
| - } |
| case MSR_STAR: |
| msr_info->data = svm->vmcb->save.star; |
| break; |
| @@ -4080,9 +4074,6 @@ static int svm_set_msr(struct kvm_vcpu * |
| svm->vmcb->save.g_pat = data; |
| mark_dirty(svm->vmcb, VMCB_NPT); |
| break; |
| - case MSR_IA32_TSC: |
| - kvm_write_tsc(vcpu, msr); |
| - break; |
| case MSR_IA32_SPEC_CTRL: |
| if (!msr->host_initiated && |
| !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS)) |
| --- a/arch/x86/kvm/vmx.c |
| +++ b/arch/x86/kvm/vmx.c |
| @@ -2650,20 +2650,6 @@ static u64 vmx_read_l1_tsc_offset(struct |
| } |
| |
| /* |
| - * reads and returns guest's timestamp counter "register" |
| - * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset |
| - * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3 |
| - */ |
| -static u64 guest_read_tsc(struct kvm_vcpu *vcpu) |
| -{ |
| - u64 host_tsc, tsc_offset; |
| - |
| - host_tsc = rdtsc(); |
| - tsc_offset = vmcs_read64(TSC_OFFSET); |
| - return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset; |
| -} |
| - |
| -/* |
| * writes 'offset' into guest's timestamp counter offset register |
| */ |
| static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) |
| @@ -3283,9 +3269,6 @@ static int vmx_get_msr(struct kvm_vcpu * |
| #endif |
| case MSR_EFER: |
| return kvm_get_msr_common(vcpu, msr_info); |
| - case MSR_IA32_TSC: |
| - msr_info->data = guest_read_tsc(vcpu); |
| - break; |
| case MSR_IA32_SPEC_CTRL: |
| if (!msr_info->host_initiated && |
| !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) |
| @@ -3403,9 +3386,6 @@ static int vmx_set_msr(struct kvm_vcpu * |
| return 1; |
| vmcs_write64(GUEST_BNDCFGS, data); |
| break; |
| - case MSR_IA32_TSC: |
| - kvm_write_tsc(vcpu, msr_info); |
| - break; |
| case MSR_IA32_SPEC_CTRL: |
| if (!msr_info->host_initiated && |
| !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) |
| --- a/arch/x86/kvm/x86.c |
| +++ b/arch/x86/kvm/x86.c |
| @@ -2333,6 +2333,9 @@ int kvm_set_msr_common(struct kvm_vcpu * |
| return 1; |
| vcpu->arch.smbase = data; |
| break; |
| + case MSR_IA32_TSC: |
| + kvm_write_tsc(vcpu, msr_info); |
| + break; |
| case MSR_SMI_COUNT: |
| if (!msr_info->host_initiated) |
| return 1; |
| @@ -2572,6 +2575,9 @@ int kvm_get_msr_common(struct kvm_vcpu * |
| case MSR_IA32_UCODE_REV: |
| msr_info->data = vcpu->arch.microcode_version; |
| break; |
| + case MSR_IA32_TSC: |
| + msr_info->data = kvm_scale_tsc(vcpu, rdtsc()) + vcpu->arch.tsc_offset; |
| + break; |
| case MSR_MTRRcap: |
| case 0x200 ... 0x2ff: |
| return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data); |