| From foo@baz Sun Jun 17 12:07:34 CEST 2018 |
| From: Mika Westerberg <mika.westerberg@linux.intel.com> |
| Date: Wed, 25 Apr 2018 13:32:11 +0300 |
| Subject: pinctrl: cherryview: Associate IRQ descriptors to irqdomain |
| |
| From: Mika Westerberg <mika.westerberg@linux.intel.com> |
| |
| [ Upstream commit 83b9dc11312f48a561594a895672abb6cb2a2250 ] |
| |
| When we dropped the custom Linux GPIO translation it resulted that the |
| IRQ numbers changed slightly as well. Normally this would be fine |
| because everyone is expected to use controller relative GPIO numbers and |
| ACPI GpioIo/GpioInt resources. However, there is a certain set of |
| Intel_Strago based Chromebooks where i8042 keyboard controller IRQ |
| number is hardcoded be 182 (this is corrected with newer coreboot but |
| the older ones still have the hardcoded Linux IRQ number). Because of |
| this hardcoded IRQ number keyboard on those systems accidentally broke |
| again. |
| |
| Fix this by iteratively associating IRQ descriptors to the chip irqdomain |
| so that there are no gaps on those systems. Other systems are not |
| affected. |
| |
| Fixes: 03c4749dd6c7 ("gpio / ACPI: Drop unnecessary ACPI GPIO to Linux GPIO translation") |
| Link: https://bugzilla.kernel.org/show_bug.cgi?id=199463 |
| Reported-by: Sultan Alsawaf <sultanxda@gmail.com> |
| Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> |
| Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> |
| Signed-off-by: Linus Walleij <linus.walleij@linaro.org> |
| Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/pinctrl/intel/pinctrl-cherryview.c | 16 ++++++++++++---- |
| 1 file changed, 12 insertions(+), 4 deletions(-) |
| |
| --- a/drivers/pinctrl/intel/pinctrl-cherryview.c |
| +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c |
| @@ -1622,22 +1622,30 @@ static int chv_gpio_probe(struct chv_pin |
| |
| if (!need_valid_mask) { |
| irq_base = devm_irq_alloc_descs(pctrl->dev, -1, 0, |
| - chip->ngpio, NUMA_NO_NODE); |
| + community->npins, NUMA_NO_NODE); |
| if (irq_base < 0) { |
| dev_err(pctrl->dev, "Failed to allocate IRQ numbers\n"); |
| return irq_base; |
| } |
| - } else { |
| - irq_base = 0; |
| } |
| |
| - ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, irq_base, |
| + ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0, |
| handle_bad_irq, IRQ_TYPE_NONE); |
| if (ret) { |
| dev_err(pctrl->dev, "failed to add IRQ chip\n"); |
| return ret; |
| } |
| |
| + if (!need_valid_mask) { |
| + for (i = 0; i < community->ngpio_ranges; i++) { |
| + range = &community->gpio_ranges[i]; |
| + |
| + irq_domain_associate_many(chip->irq.domain, irq_base, |
| + range->base, range->npins); |
| + irq_base += range->npins; |
| + } |
| + } |
| + |
| gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq, |
| chv_gpio_irq_handler); |
| return 0; |