| From foo@baz Sun Jun 17 12:07:33 CEST 2018 |
| From: "jacek.tomaka@poczta.fm" <jacek.tomaka@poczta.fm> |
| Date: Tue, 24 Apr 2018 00:14:25 +0800 |
| Subject: x86/cpu/intel: Add missing TLB cpuid values |
| |
| From: "jacek.tomaka@poczta.fm" <jacek.tomaka@poczta.fm> |
| |
| [ Upstream commit b837913fc2d9061bf9b8c0dd6bf2d24e2f98b84a ] |
| |
| Make kernel print the correct number of TLB entries on Intel Xeon Phi 7210 |
| (and others) |
| |
| Before: |
| [ 0.320005] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0 |
| After: |
| [ 0.320005] Last level dTLB entries: 4KB 256, 2MB 128, 4MB 128, 1GB 16 |
| |
| The entries do exist in the official Intel SMD but the type column there is |
| incorrect (states "Cache" where it should read "TLB"), but the entries for |
| the values 0x6B, 0x6C and 0x6D are correctly described as 'Data TLB'. |
| |
| Signed-off-by: Jacek Tomaka <jacek.tomaka@poczta.fm> |
| Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
| Link: https://lkml.kernel.org/r/20180423161425.24366-1-jacekt@dugeo.com |
| Signed-off-by: Sasha Levin <alexander.levin@microsoft.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/x86/kernel/cpu/intel.c | 3 +++ |
| 1 file changed, 3 insertions(+) |
| |
| --- a/arch/x86/kernel/cpu/intel.c |
| +++ b/arch/x86/kernel/cpu/intel.c |
| @@ -751,6 +751,9 @@ static const struct _tlb_table intel_tlb |
| { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, |
| { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, |
| { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, |
| + { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" }, |
| + { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" }, |
| + { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" }, |
| { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, |
| { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, |
| { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" }, |