| From 2ed2d4bf3749d9aaefce47841e21f58a9ed2733e Mon Sep 17 00:00:00 2001 |
| From: Taniya Das <tdas@codeaurora.org> |
| Date: Tue, 18 Dec 2018 23:49:41 +0530 |
| Subject: clk: qcom: gcc: Use active only source for CPUSS clocks |
| |
| [ Upstream commit 9ff1a3b4912528f853048ccd9757ba6a2cc75557 ] |
| |
| The clocks of the CPUSS such as "gcc_cpuss_ahb_clk_src" is a CRITICAL |
| clock and needs to vote on the active only source of XO, so as to keep |
| the vote as long as CPUSS is active. Similar rbcpr_clk_src is also has |
| the same requirement. |
| |
| Signed-off-by: Taniya Das <tdas@codeaurora.org> |
| Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845") |
| Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/clk/qcom/gcc-sdm845.c | 14 ++++++++++---- |
| 1 file changed, 10 insertions(+), 4 deletions(-) |
| |
| diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c |
| index fa1a196350f1..3bf11a620094 100644 |
| --- a/drivers/clk/qcom/gcc-sdm845.c |
| +++ b/drivers/clk/qcom/gcc-sdm845.c |
| @@ -131,8 +131,8 @@ static const char * const gcc_parent_names_6[] = { |
| "core_bi_pll_test_se", |
| }; |
| |
| -static const char * const gcc_parent_names_7[] = { |
| - "bi_tcxo", |
| +static const char * const gcc_parent_names_7_ao[] = { |
| + "bi_tcxo_ao", |
| "gpll0", |
| "gpll0_out_even", |
| "core_bi_pll_test_se", |
| @@ -144,6 +144,12 @@ static const char * const gcc_parent_names_8[] = { |
| "core_bi_pll_test_se", |
| }; |
| |
| +static const char * const gcc_parent_names_8_ao[] = { |
| + "bi_tcxo_ao", |
| + "gpll0", |
| + "core_bi_pll_test_se", |
| +}; |
| + |
| static const struct parent_map gcc_parent_map_10[] = { |
| { P_BI_TCXO, 0 }, |
| { P_GPLL0_OUT_MAIN, 1 }, |
| @@ -226,7 +232,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { |
| .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "gcc_cpuss_ahb_clk_src", |
| - .parent_names = gcc_parent_names_7, |
| + .parent_names = gcc_parent_names_7_ao, |
| .num_parents = 4, |
| .ops = &clk_rcg2_ops, |
| }, |
| @@ -245,7 +251,7 @@ static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = { |
| .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src, |
| .clkr.hw.init = &(struct clk_init_data){ |
| .name = "gcc_cpuss_rbcpr_clk_src", |
| - .parent_names = gcc_parent_names_8, |
| + .parent_names = gcc_parent_names_8_ao, |
| .num_parents = 3, |
| .ops = &clk_rcg2_ops, |
| }, |
| -- |
| 2.19.1 |
| |