| From foo@baz Tue Mar 12 09:27:32 PDT 2019 |
| From: "Peter Zijlstra (Intel)" <peterz@infradead.org> |
| Date: Tue, 5 Mar 2019 22:23:17 +0100 |
| Subject: x86: Add TSX Force Abort CPUID/MSR |
| |
| From: "Peter Zijlstra (Intel)" <peterz@infradead.org> |
| |
| commit 52f64909409c17adf54fcf5f9751e0544ca3a6b4 upstream |
| |
| Skylake systems will receive a microcode update to address a TSX |
| errata. This microcode will (by default) clobber PMC3 when TSX |
| instructions are (speculatively or not) executed. |
| |
| It also provides an MSR to cause all TSX transaction to abort and |
| preserve PMC3. |
| |
| Add the CPUID enumeration and MSR definition. |
| |
| Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> |
| Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/x86/include/asm/cpufeatures.h | 1 + |
| arch/x86/include/asm/msr-index.h | 6 ++++++ |
| 2 files changed, 7 insertions(+) |
| |
| --- a/arch/x86/include/asm/cpufeatures.h |
| +++ b/arch/x86/include/asm/cpufeatures.h |
| @@ -340,6 +340,7 @@ |
| /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ |
| #define X86_FEATURE_AVX512_4VNNIW (18*32+ 2) /* AVX-512 Neural Network Instructions */ |
| #define X86_FEATURE_AVX512_4FMAPS (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */ |
| +#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */ |
| #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ |
| #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ |
| #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ |
| --- a/arch/x86/include/asm/msr-index.h |
| +++ b/arch/x86/include/asm/msr-index.h |
| @@ -629,6 +629,12 @@ |
| |
| #define MSR_IA32_TSC_DEADLINE 0x000006E0 |
| |
| + |
| +#define MSR_TSX_FORCE_ABORT 0x0000010F |
| + |
| +#define MSR_TFA_RTM_FORCE_ABORT_BIT 0 |
| +#define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) |
| + |
| /* P4/Xeon+ specific */ |
| #define MSR_IA32_MCG_EAX 0x00000180 |
| #define MSR_IA32_MCG_EBX 0x00000181 |