| From 2e095ce7b6ecce2f3e2ff330527f12056ed1e1a1 Mon Sep 17 00:00:00 2001 |
| From: Alexander Shishkin <alexander.shishkin@linux.intel.com> |
| Date: Thu, 7 Feb 2019 15:30:05 +0200 |
| Subject: x86/PCI: Fixup RTIT_BAR of Intel Denverton Trace Hub |
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| |
| From: Alexander Shishkin <alexander.shishkin@linux.intel.com> |
| |
| commit 2e095ce7b6ecce2f3e2ff330527f12056ed1e1a1 upstream. |
| |
| On Denverton's integration of the Intel(R) Trace Hub (for a reference and |
| overview see Documentation/trace/intel_th.rst) the reported size of one of |
| its resources (RTIT_BAR) doesn't match its actual size, which leads to |
| overlaps with other devices' resources. |
| |
| In practice, it overlaps with XHCI MMIO space, which results in the xhci |
| driver bailing out after seeing its registers as 0xffffffff, and perceived |
| disappearance of all USB devices: |
| |
| intel_th_pci 0000:00:1f.7: enabling device (0004 -> 0006) |
| xhci_hcd 0000:00:15.0: xHCI host controller not responding, assume dead |
| xhci_hcd 0000:00:15.0: xHC not responding in xhci_irq, assume controller is dead |
| xhci_hcd 0000:00:15.0: HC died; cleaning up |
| usb 1-1: USB disconnect, device number 2 |
| |
| For this reason, we need to resize the RTIT_BAR on Denverton to its actual |
| size, which in this case is 4MB. The corresponding erratum is DNV36 at the |
| link below: |
| |
| DNV36. Processor Host Root Complex May Incorrectly Route Memory |
| Accesses to Intel® Trace Hub |
| |
| Problem: The Intel® Trace Hub RTIT_BAR (B0:D31:F7 offset 20h) is |
| reported as a 2KB memory range. Due to this erratum, the |
| processor Host Root Complex will forward addresses from |
| RTIT_BAR to RTIT_BAR + 4MB -1 to Intel® Trace Hub. |
| |
| Implication: Devices assigned within the RTIT_BAR to RTIT_BAR + 4MB -1 |
| space may not function correctly. |
| |
| Workaround: A BIOS code change has been identified and may be |
| implemented as a workaround for this erratum. |
| |
| Status: No Fix. |
| |
| Note that 5118ccd34780 ("intel_th: pci: Add Denverton SOC support") updates |
| the Trace Hub driver so it claims the Denverton device, but the resource |
| overlap exists regardless of whether that driver is loaded or that commit |
| is included. |
| |
| Link: https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/atom-c3000-family-spec-update.pdf |
| Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> |
| [bhelgaas: include erratum text, clarify relationship with 5118ccd34780] |
| Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/x86/pci/fixup.c | 16 ++++++++++++++++ |
| 1 file changed, 16 insertions(+) |
| |
| --- a/arch/x86/pci/fixup.c |
| +++ b/arch/x86/pci/fixup.c |
| @@ -641,6 +641,22 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IN |
| DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x334c, quirk_no_aersid); |
| DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x334d, quirk_no_aersid); |
| |
| +static void quirk_intel_th_dnv(struct pci_dev *dev) |
| +{ |
| + struct resource *r = &dev->resource[4]; |
| + |
| + /* |
| + * Denverton reports 2k of RTIT_BAR (intel_th resource 4), which |
| + * appears to be 4 MB in reality. |
| + */ |
| + if (r->end == r->start + 0x7ff) { |
| + r->start = 0; |
| + r->end = 0x3fffff; |
| + r->flags |= IORESOURCE_UNSET; |
| + } |
| +} |
| +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x19e1, quirk_intel_th_dnv); |
| + |
| #ifdef CONFIG_PHYS_ADDR_T_64BIT |
| |
| #define AMD_141b_MMIO_BASE(x) (0x80 + (x) * 0x8) |