| From bb98e72adaf9d19719aba35f802d4836f5d5176c Mon Sep 17 00:00:00 2001 |
| From: Hans de Goede <hdegoede@redhat.com> |
| Date: Fri, 2 Dec 2016 15:29:04 +0100 |
| Subject: drm/i915/dsi: Do not clear DPOUNIT_CLOCK_GATE_DISABLE from vlv_init_display_clock_gating |
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| From: Hans de Goede <hdegoede@redhat.com> |
| |
| commit bb98e72adaf9d19719aba35f802d4836f5d5176c upstream. |
| |
| On my Cherrytrail CUBE iwork8 Air tablet PIPE-A would get stuck on loading |
| i915 at boot 1 out of every 3 boots, resulting in a non functional LCD. |
| Once the i915 driver has successfully loaded, the panel can be disabled / |
| enabled without hitting this issue. |
| |
| The getting stuck is caused by vlv_init_display_clock_gating() clearing |
| the DPOUNIT_CLOCK_GATE_DISABLE bit in DSPCLK_GATE_D when called from |
| chv_pipe_power_well_ops.enable() on driver load, while a pipe is enabled |
| driving the DSI LCD by the BIOS. |
| |
| Clearing this bit while DSI is in use is a known issue and |
| intel_dsi_pre_enable() / intel_dsi_post_disable() already set / clear it |
| as appropriate. |
| |
| This commit modifies vlv_init_display_clock_gating() to leave the |
| DPOUNIT_CLOCK_GATE_DISABLE bit alone fixing the pipe getting stuck. |
| |
| Changes in v2: |
| -Replace PIPE-A with "a pipe" or "the pipe" in the commit msg and |
| comment |
| |
| Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97330 |
| Signed-off-by: Hans de Goede <hdegoede@redhat.com> |
| Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| Link: http://patchwork.freedesktop.org/patch/msgid/20161202142904.25613-1-hdegoede@redhat.com |
| Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> |
| (cherry picked from commit 721d484563e1a51ada760089c490cbc47e909756) |
| Signed-off-by: Jani Nikula <jani.nikula@intel.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++++++++++++- |
| 1 file changed, 12 insertions(+), 1 deletion(-) |
| |
| --- a/drivers/gpu/drm/i915/intel_runtime_pm.c |
| +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c |
| @@ -1062,7 +1062,18 @@ static bool vlv_power_well_enabled(struc |
| |
| static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) |
| { |
| - I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
| + u32 val; |
| + |
| + /* |
| + * On driver load, a pipe may be active and driving a DSI display. |
| + * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck |
| + * (and never recovering) in this case. intel_dsi_post_disable() will |
| + * clear it when we turn off the display. |
| + */ |
| + val = I915_READ(DSPCLK_GATE_D); |
| + val &= DPOUNIT_CLOCK_GATE_DISABLE; |
| + val |= VRHUNIT_CLOCK_GATE_DISABLE; |
| + I915_WRITE(DSPCLK_GATE_D, val); |
| |
| /* |
| * Disable trickle feed and enable pnd deadline calculation |