| From foo@baz Tue Aug 14 16:14:56 CEST 2018 |
| From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> |
| Date: Wed, 20 Jun 2018 16:42:58 -0400 |
| Subject: x86/cpufeatures: Add detection of L1D cache flush support. |
| |
| From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> |
| |
| commit 11e34e64e4103955fc4568750914c75d65ea87ee upstream |
| |
| 336996-Speculative-Execution-Side-Channel-Mitigations.pdf defines a new MSR |
| (IA32_FLUSH_CMD) which is detected by CPUID.7.EDX[28]=1 bit being set. |
| |
| This new MSR "gives software a way to invalidate structures with finer |
| granularity than other architectual methods like WBINVD." |
| |
| A copy of this document is available at |
| https://bugzilla.kernel.org/show_bug.cgi?id=199511 |
| |
| Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> |
| Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
| Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/x86/include/asm/cpufeatures.h | 1 + |
| 1 file changed, 1 insertion(+) |
| |
| --- a/arch/x86/include/asm/cpufeatures.h |
| +++ b/arch/x86/include/asm/cpufeatures.h |
| @@ -317,6 +317,7 @@ |
| #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ |
| #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ |
| #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ |
| +#define X86_FEATURE_FLUSH_L1D (18*32+28) /* Flush L1D cache */ |
| #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ |
| #define X86_FEATURE_SPEC_CTRL_SSBD (18*32+31) /* "" Speculative Store Bypass Disable */ |
| |
