| From 4c5c240d9003591261525828172905ed9939434a Mon Sep 17 00:00:00 2001 |
| From: Andrzej Pietrasiewicz <andrzej.p@samsung.com> |
| Date: Fri, 29 Sep 2017 09:32:53 +0200 |
| Subject: clk: samsung: Fix m2m scaler clock on Exynos542x |
| |
| [ Upstream commit c07c1a0f68d0f2f7ca9aff924e2772526027b019 ] |
| |
| The TOP "aclk400_mscl" clock should be kept enabled all the time |
| to allow proper access to power management control for MSC power |
| domain and devices that are a part of it. This change is required |
| for the scaler to work properly after domain power on/off sequence. |
| |
| Fixes: 318fa46cc60d ("clk/samsung: exynos542x: mark some clocks as critical") |
| Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com> |
| Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> |
| Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/clk/samsung/clk-exynos5420.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c |
| index cdc092a1d9ef..07fb667e258f 100644 |
| --- a/drivers/clk/samsung/clk-exynos5420.c |
| +++ b/drivers/clk/samsung/clk-exynos5420.c |
| @@ -987,7 +987,7 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { |
| GATE(0, "aclk400_isp", "mout_user_aclk400_isp", |
| GATE_BUS_TOP, 16, 0, 0), |
| GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl", |
| - GATE_BUS_TOP, 17, 0, 0), |
| + GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0), |
| GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1", |
| GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0), |
| GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24", |
| -- |
| 2.17.1 |
| |