| From foo@baz Sun Dec 31 11:13:15 CET 2017 |
| From: Eran Ben Elisha <eranbe@mellanox.com> |
| Date: Mon, 13 Nov 2017 10:11:27 +0200 |
| Subject: net/mlx5: Fix rate limit packet pacing naming and struct |
| |
| From: Eran Ben Elisha <eranbe@mellanox.com> |
| |
| |
| [ Upstream commit 37e92a9d4fe38dc3e7308913575983a6a088c8d4 ] |
| |
| In mlx5_ifc, struct size was not complete, and thus driver was sending |
| garbage after the last defined field. Fixed it by adding reserved field |
| to complete the struct size. |
| |
| In addition, rename all set_rate_limit to set_pp_rate_limit to be |
| compliant with the Firmware <-> Driver definition. |
| |
| Fixes: 7486216b3a0b ("{net,IB}/mlx5: mlx5_ifc updates") |
| Fixes: 1466cc5b23d1 ("net/mlx5: Rate limit tables support") |
| Signed-off-by: Eran Ben Elisha <eranbe@mellanox.com> |
| Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/net/ethernet/mellanox/mlx5/core/cmd.c | 4 ++-- |
| drivers/net/ethernet/mellanox/mlx5/core/rl.c | 22 +++++++++++----------- |
| include/linux/mlx5/mlx5_ifc.h | 8 +++++--- |
| 3 files changed, 18 insertions(+), 16 deletions(-) |
| |
| --- a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c |
| +++ b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c |
| @@ -367,7 +367,7 @@ static int mlx5_internal_err_ret_value(s |
| case MLX5_CMD_OP_QUERY_VPORT_COUNTER: |
| case MLX5_CMD_OP_ALLOC_Q_COUNTER: |
| case MLX5_CMD_OP_QUERY_Q_COUNTER: |
| - case MLX5_CMD_OP_SET_RATE_LIMIT: |
| + case MLX5_CMD_OP_SET_PP_RATE_LIMIT: |
| case MLX5_CMD_OP_QUERY_RATE_LIMIT: |
| case MLX5_CMD_OP_ALLOC_PD: |
| case MLX5_CMD_OP_ALLOC_UAR: |
| @@ -502,7 +502,7 @@ const char *mlx5_command_str(int command |
| MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER); |
| MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER); |
| MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER); |
| - MLX5_COMMAND_STR_CASE(SET_RATE_LIMIT); |
| + MLX5_COMMAND_STR_CASE(SET_PP_RATE_LIMIT); |
| MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT); |
| MLX5_COMMAND_STR_CASE(ALLOC_PD); |
| MLX5_COMMAND_STR_CASE(DEALLOC_PD); |
| --- a/drivers/net/ethernet/mellanox/mlx5/core/rl.c |
| +++ b/drivers/net/ethernet/mellanox/mlx5/core/rl.c |
| @@ -60,16 +60,16 @@ static struct mlx5_rl_entry *find_rl_ent |
| return ret_entry; |
| } |
| |
| -static int mlx5_set_rate_limit_cmd(struct mlx5_core_dev *dev, |
| +static int mlx5_set_pp_rate_limit_cmd(struct mlx5_core_dev *dev, |
| u32 rate, u16 index) |
| { |
| - u32 in[MLX5_ST_SZ_DW(set_rate_limit_in)] = {0}; |
| - u32 out[MLX5_ST_SZ_DW(set_rate_limit_out)] = {0}; |
| + u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)] = {0}; |
| + u32 out[MLX5_ST_SZ_DW(set_pp_rate_limit_out)] = {0}; |
| |
| - MLX5_SET(set_rate_limit_in, in, opcode, |
| - MLX5_CMD_OP_SET_RATE_LIMIT); |
| - MLX5_SET(set_rate_limit_in, in, rate_limit_index, index); |
| - MLX5_SET(set_rate_limit_in, in, rate_limit, rate); |
| + MLX5_SET(set_pp_rate_limit_in, in, opcode, |
| + MLX5_CMD_OP_SET_PP_RATE_LIMIT); |
| + MLX5_SET(set_pp_rate_limit_in, in, rate_limit_index, index); |
| + MLX5_SET(set_pp_rate_limit_in, in, rate_limit, rate); |
| return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out)); |
| } |
| |
| @@ -108,7 +108,7 @@ int mlx5_rl_add_rate(struct mlx5_core_de |
| entry->refcount++; |
| } else { |
| /* new rate limit */ |
| - err = mlx5_set_rate_limit_cmd(dev, rate, entry->index); |
| + err = mlx5_set_pp_rate_limit_cmd(dev, rate, entry->index); |
| if (err) { |
| mlx5_core_err(dev, "Failed configuring rate: %u (%d)\n", |
| rate, err); |
| @@ -144,7 +144,7 @@ void mlx5_rl_remove_rate(struct mlx5_cor |
| entry->refcount--; |
| if (!entry->refcount) { |
| /* need to remove rate */ |
| - mlx5_set_rate_limit_cmd(dev, 0, entry->index); |
| + mlx5_set_pp_rate_limit_cmd(dev, 0, entry->index); |
| entry->rate = 0; |
| } |
| |
| @@ -197,8 +197,8 @@ void mlx5_cleanup_rl_table(struct mlx5_c |
| /* Clear all configured rates */ |
| for (i = 0; i < table->max_size; i++) |
| if (table->rl_entry[i].rate) |
| - mlx5_set_rate_limit_cmd(dev, 0, |
| - table->rl_entry[i].index); |
| + mlx5_set_pp_rate_limit_cmd(dev, 0, |
| + table->rl_entry[i].index); |
| |
| kfree(dev->priv.rl_table.rl_entry); |
| } |
| --- a/include/linux/mlx5/mlx5_ifc.h |
| +++ b/include/linux/mlx5/mlx5_ifc.h |
| @@ -143,7 +143,7 @@ enum { |
| MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, |
| MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, |
| MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, |
| - MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, |
| + MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, |
| MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, |
| MLX5_CMD_OP_ALLOC_PD = 0x800, |
| MLX5_CMD_OP_DEALLOC_PD = 0x801, |
| @@ -6689,7 +6689,7 @@ struct mlx5_ifc_add_vxlan_udp_dport_in_b |
| u8 vxlan_udp_port[0x10]; |
| }; |
| |
| -struct mlx5_ifc_set_rate_limit_out_bits { |
| +struct mlx5_ifc_set_pp_rate_limit_out_bits { |
| u8 status[0x8]; |
| u8 reserved_at_8[0x18]; |
| |
| @@ -6698,7 +6698,7 @@ struct mlx5_ifc_set_rate_limit_out_bits |
| u8 reserved_at_40[0x40]; |
| }; |
| |
| -struct mlx5_ifc_set_rate_limit_in_bits { |
| +struct mlx5_ifc_set_pp_rate_limit_in_bits { |
| u8 opcode[0x10]; |
| u8 reserved_at_10[0x10]; |
| |
| @@ -6711,6 +6711,8 @@ struct mlx5_ifc_set_rate_limit_in_bits { |
| u8 reserved_at_60[0x20]; |
| |
| u8 rate_limit[0x20]; |
| + |
| + u8 reserved_at_a0[0x160]; |
| }; |
| |
| struct mlx5_ifc_access_register_out_bits { |