| From 866483e59ad88f1e0e54da0e299c11b1439753b3 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Fri, 17 Sep 2021 18:14:14 +0800 |
| Subject: i2c: mediatek: Add OFFSET_EXT_CONF setting back |
| |
| From: Kewei Xu <kewei.xu@mediatek.com> |
| |
| [ Upstream commit 3bce7703c7ba648bd9e174dc1413f422b7998833 ] |
| |
| In the commit be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust |
| support"), we miss setting OFFSET_EXT_CONF register if |
| i2c->dev_comp->timing_adjust is false, now add it back. |
| |
| Fixes: be5ce0e97cc7 ("i2c: mediatek: Add i2c ac-timing adjust support") |
| Signed-off-by: Kewei Xu <kewei.xu@mediatek.com> |
| Reviewed-by: Qii Wang <qii.wang@mediatek.com> |
| Signed-off-by: Wolfram Sang <wsa@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/i2c/busses/i2c-mt65xx.c | 11 ++++++++++- |
| 1 file changed, 10 insertions(+), 1 deletion(-) |
| |
| diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c |
| index 1a5f1ccd1d2f..0af2784cbd0d 100644 |
| --- a/drivers/i2c/busses/i2c-mt65xx.c |
| +++ b/drivers/i2c/busses/i2c-mt65xx.c |
| @@ -41,6 +41,8 @@ |
| #define I2C_HANDSHAKE_RST 0x0020 |
| #define I2C_FIFO_ADDR_CLR 0x0001 |
| #define I2C_DELAY_LEN 0x0002 |
| +#define I2C_ST_START_CON 0x8001 |
| +#define I2C_FS_START_CON 0x1800 |
| #define I2C_TIME_CLR_VALUE 0x0000 |
| #define I2C_TIME_DEFAULT_VALUE 0x0003 |
| #define I2C_WRRD_TRANAC_VALUE 0x0002 |
| @@ -479,6 +481,7 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c) |
| { |
| u16 control_reg; |
| u16 intr_stat_reg; |
| + u16 ext_conf_val; |
| |
| mtk_i2c_writew(i2c, I2C_CHN_CLR_FLAG, OFFSET_START); |
| intr_stat_reg = mtk_i2c_readw(i2c, OFFSET_INTR_STAT); |
| @@ -517,8 +520,13 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c) |
| if (i2c->dev_comp->ltiming_adjust) |
| mtk_i2c_writew(i2c, i2c->ltiming_reg, OFFSET_LTIMING); |
| |
| + if (i2c->speed_hz <= I2C_MAX_STANDARD_MODE_FREQ) |
| + ext_conf_val = I2C_ST_START_CON; |
| + else |
| + ext_conf_val = I2C_FS_START_CON; |
| + |
| if (i2c->dev_comp->timing_adjust) { |
| - mtk_i2c_writew(i2c, i2c->ac_timing.ext, OFFSET_EXT_CONF); |
| + ext_conf_val = i2c->ac_timing.ext; |
| mtk_i2c_writew(i2c, i2c->ac_timing.inter_clk_div, |
| OFFSET_CLOCK_DIV); |
| mtk_i2c_writew(i2c, I2C_SCL_MIS_COMP_VALUE, |
| @@ -543,6 +551,7 @@ static void mtk_i2c_init_hw(struct mtk_i2c *i2c) |
| OFFSET_HS_STA_STO_AC_TIMING); |
| } |
| } |
| + mtk_i2c_writew(i2c, ext_conf_val, OFFSET_EXT_CONF); |
| |
| /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */ |
| if (i2c->have_pmic) |
| -- |
| 2.33.0 |
| |