| From a8383dfb2138742a1bb77b481ada047aededa2ba Mon Sep 17 00:00:00 2001 |
| From: CodyYao-oc <CodyYao-oc@zhaoxin.com> |
| Date: Mon, 7 Jun 2021 10:53:35 +0800 |
| Subject: x86/nmi_watchdog: Fix old-style NMI watchdog regression on old Intel CPUs |
| |
| From: CodyYao-oc <CodyYao-oc@zhaoxin.com> |
| |
| commit a8383dfb2138742a1bb77b481ada047aededa2ba upstream. |
| |
| The following commit: |
| |
| 3a4ac121c2ca ("x86/perf: Add hardware performance events support for Zhaoxin CPU.") |
| |
| Got the old-style NMI watchdog logic wrong and broke it for basically every |
| Intel CPU where it was active. Which is only truly old CPUs, so few people noticed. |
| |
| On CPUs with perf events support we turn off the old-style NMI watchdog, so it |
| was pretty pointless to add the logic for X86_VENDOR_ZHAOXIN to begin with ... :-/ |
| |
| Anyway, the fix is to restore the old logic and add a 'break'. |
| |
| [ mingo: Wrote a new changelog. ] |
| |
| Fixes: 3a4ac121c2ca ("x86/perf: Add hardware performance events support for Zhaoxin CPU.") |
| Signed-off-by: CodyYao-oc <CodyYao-oc@zhaoxin.com> |
| Signed-off-by: Ingo Molnar <mingo@kernel.org> |
| Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> |
| Link: https://lore.kernel.org/r/20210607025335.9643-1-CodyYao-oc@zhaoxin.com |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/x86/kernel/cpu/perfctr-watchdog.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| --- a/arch/x86/kernel/cpu/perfctr-watchdog.c |
| +++ b/arch/x86/kernel/cpu/perfctr-watchdog.c |
| @@ -63,7 +63,7 @@ static inline unsigned int nmi_perfctr_m |
| case 15: |
| return msr - MSR_P4_BPU_PERFCTR0; |
| } |
| - fallthrough; |
| + break; |
| case X86_VENDOR_ZHAOXIN: |
| case X86_VENDOR_CENTAUR: |
| return msr - MSR_ARCH_PERFMON_PERFCTR0; |
| @@ -96,7 +96,7 @@ static inline unsigned int nmi_evntsel_m |
| case 15: |
| return msr - MSR_P4_BSU_ESCR0; |
| } |
| - fallthrough; |
| + break; |
| case X86_VENDOR_ZHAOXIN: |
| case X86_VENDOR_CENTAUR: |
| return msr - MSR_ARCH_PERFMON_EVENTSEL0; |