| From ed7d29d4bc5ff563999f770b333397a4d8689cd2 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Fri, 9 Apr 2021 01:00:01 +0200 |
| Subject: ARM: dts: stm32: Rework LAN8710Ai PHY reset on DHCOM SoM |
| |
| From: Marek Vasut <marex@denx.de> |
| |
| [ Upstream commit 1cebcf9932ab76102e8cfc555879574693ba8956 ] |
| |
| The Microchip LAN8710Ai PHY requires XTAL1/CLKIN external clock to be |
| enabled when the nRST is toggled according to datasheet Microchip |
| LAN8710A/LAN8710Ai DS00002164B page 35 section 3.8.5.1 Hardware Reset: |
| " |
| A Hardware reset is asserted by driving the nRST input pin low. When |
| driven, nRST should be held low for the minimum time detailed in |
| Section 5.5.3, "Power-On nRST & Configuration Strap Timing," on page |
| 59 to ensure a proper transceiver reset. During a Hardware reset, an |
| external clock must be supplied to the XTAL1/CLKIN signal. |
| " |
| This is accidentally fulfilled in the current setup, where ETHCK_K is used |
| to supply both PHY XTAL1/CLKIN and is also fed back through eth_clk_fb to |
| supply ETHRX clock of the DWMAC. Hence, the DWMAC enables ETHRX clock, |
| that has ETHCK_K as parent, so ETHCK_K clock are also enabled, and then |
| the PHY reset toggles. |
| |
| However, this is not always the case, e.g. in case the PHY XTAL1/CLKIN |
| clock are supplied by some other clock source than ETHCK_K or in case |
| ETHRX clock are not supplied by ETHCK_K. In the later case, ETHCK_K would |
| be kept disabled, while ETHRX clock would be enabled, so the PHY would |
| not be receiving XTAL1/CLKIN clock and the reset would fail. |
| |
| Improve the DT by adding the PHY clock phandle into the PHY node, which |
| then also requires moving the PHY reset GPIO specifier in the same place |
| and that then also requires correct PHY reset GPIO timing, so add that |
| too. |
| |
| A brief note regarding the timing, the datasheet says the reset should |
| stay asserted for at least 100uS and software should wait at least 200nS |
| after deassertion. Set both delays to 500uS which should be plenty. |
| |
| Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") |
| Signed-off-by: Marek Vasut <marex@denx.de> |
| Cc: Alexandre Torgue <alexandre.torgue@st.com> |
| Cc: Patrice Chotard <patrice.chotard@st.com> |
| Cc: Patrick Delaunay <patrick.delaunay@st.com> |
| Cc: linux-stm32@st-md-mailman.stormreply.com |
| To: linux-arm-kernel@lists.infradead.org |
| Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 8 +++++++- |
| 1 file changed, 7 insertions(+), 1 deletion(-) |
| |
| diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi |
| index 2617815e42a6..30e4d990c5a3 100644 |
| --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi |
| +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi |
| @@ -119,7 +119,6 @@ |
| max-speed = <100>; |
| phy-handle = <&phy0>; |
| st,eth-ref-clk-sel; |
| - phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; |
| |
| mdio0 { |
| #address-cells = <1>; |
| @@ -128,6 +127,13 @@ |
| |
| phy0: ethernet-phy@1 { |
| reg = <1>; |
| + /* LAN8710Ai */ |
| + compatible = "ethernet-phy-id0007.c0f0", |
| + "ethernet-phy-ieee802.3-c22"; |
| + clocks = <&rcc ETHCK_K>; |
| + reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; |
| + reset-assert-us = <500>; |
| + reset-deassert-us = <500>; |
| interrupt-parent = <&gpioi>; |
| interrupts = <11 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| -- |
| 2.30.2 |
| |