| From 4e39fabb24d58b2099eb863fcaedc159204e4818 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Wed, 9 Jun 2021 16:38:43 +0800 |
| Subject: arm64: dts: allwinner: a64-sopine-baseboard: change RGMII mode to |
| TXID |
| |
| From: Icenowy Zheng <icenowy@aosc.io> |
| |
| [ Upstream commit bd5431b2f9b30a70f6ed964dd5ee9a6d1c397c06 ] |
| |
| Although the schematics of Pine A64-LTS and SoPine Baseboard shows both |
| the RX and TX internal delay are enabled, they're using the same broken |
| RTL8211E chip batch with Pine A64+, so they should use TXID instead, not |
| ID. |
| |
| In addition, by checking the real components soldered on both a SoPine |
| Baseboard and a Pine A64-LTS, RX delay is not enabled (GR69 soldered and |
| GR70 NC) despite the schematics says it's enabled. It's a common |
| situation for Pine64 boards that the NC information on schematics is not |
| the same with the board. |
| |
| So the RGMII delay mode should be TXID on these boards. |
| |
| Fixes: c2b111e59a7b ("arm64: dts: allwinner: A64 Sopine: phy-mode rgmii-id") |
| Signed-off-by: Icenowy Zheng <icenowy@aosc.io> |
| Signed-off-by: Maxime Ripard <maxime@cerno.tech> |
| Link: https://lore.kernel.org/r/20210609083843.463750-1-icenowy@aosc.io |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts |
| index e22b94c83647..5e66ce1a334f 100644 |
| --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts |
| +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts |
| @@ -79,7 +79,7 @@ |
| &emac { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&rgmii_pins>; |
| - phy-mode = "rgmii-id"; |
| + phy-mode = "rgmii-txid"; |
| phy-handle = <&ext_rgmii_phy>; |
| phy-supply = <®_dc1sw>; |
| status = "okay"; |
| -- |
| 2.30.2 |
| |