| From b14ce236f5b864c69e1404dfaeb9eb52077d3505 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Thu, 10 Jun 2021 14:06:39 +0530 |
| Subject: powerpc/mm/book3s64: Fix possible build error |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| From: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> |
| |
| [ Upstream commit 07d8ad6fd8a3d47f50595ca4826f41dbf4f3a0c6 ] |
| |
| Update _tlbiel_pid() such that we can avoid build errors like below when |
| using this function in other places. |
| |
| arch/powerpc/mm/book3s64/radix_tlb.c: In function ‘__radix__flush_tlb_range_psize’: |
| arch/powerpc/mm/book3s64/radix_tlb.c:114:2: warning: ‘asm’ operand 3 probably does not match constraints |
| 114 | asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1) |
| | ^~~ |
| arch/powerpc/mm/book3s64/radix_tlb.c:114:2: error: impossible constraint in ‘asm’ |
| make[4]: *** [scripts/Makefile.build:271: arch/powerpc/mm/book3s64/radix_tlb.o] Error 1 |
| m |
| |
| With this fix, we can also drop the __always_inline in __radix_flush_tlb_range_psize |
| which was added by commit e12d6d7d46a6 ("powerpc/mm/radix: mark __radix__flush_tlb_range_psize() as __always_inline") |
| |
| Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> |
| Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu> |
| Acked-by: Michael Ellerman <mpe@ellerman.id.au> |
| Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> |
| Link: https://lore.kernel.org/r/20210610083639.387365-1-aneesh.kumar@linux.ibm.com |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| arch/powerpc/mm/book3s64/radix_tlb.c | 26 +++++++++++++++++--------- |
| 1 file changed, 17 insertions(+), 9 deletions(-) |
| |
| diff --git a/arch/powerpc/mm/book3s64/radix_tlb.c b/arch/powerpc/mm/book3s64/radix_tlb.c |
| index 409e61210789..817a02ef6032 100644 |
| --- a/arch/powerpc/mm/book3s64/radix_tlb.c |
| +++ b/arch/powerpc/mm/book3s64/radix_tlb.c |
| @@ -291,22 +291,30 @@ static inline void fixup_tlbie_lpid(unsigned long lpid) |
| /* |
| * We use 128 set in radix mode and 256 set in hpt mode. |
| */ |
| -static __always_inline void _tlbiel_pid(unsigned long pid, unsigned long ric) |
| +static inline void _tlbiel_pid(unsigned long pid, unsigned long ric) |
| { |
| int set; |
| |
| asm volatile("ptesync": : :"memory"); |
| |
| - /* |
| - * Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL, |
| - * also flush the entire Page Walk Cache. |
| - */ |
| - __tlbiel_pid(pid, 0, ric); |
| + switch (ric) { |
| + case RIC_FLUSH_PWC: |
| |
| - /* For PWC, only one flush is needed */ |
| - if (ric == RIC_FLUSH_PWC) { |
| + /* For PWC, only one flush is needed */ |
| + __tlbiel_pid(pid, 0, RIC_FLUSH_PWC); |
| ppc_after_tlbiel_barrier(); |
| return; |
| + case RIC_FLUSH_TLB: |
| + __tlbiel_pid(pid, 0, RIC_FLUSH_TLB); |
| + break; |
| + case RIC_FLUSH_ALL: |
| + default: |
| + /* |
| + * Flush the first set of the TLB, and if |
| + * we're doing a RIC_FLUSH_ALL, also flush |
| + * the entire Page Walk Cache. |
| + */ |
| + __tlbiel_pid(pid, 0, RIC_FLUSH_ALL); |
| } |
| |
| if (!cpu_has_feature(CPU_FTR_ARCH_31)) { |
| @@ -1176,7 +1184,7 @@ void radix__tlb_flush(struct mmu_gather *tlb) |
| } |
| } |
| |
| -static __always_inline void __radix__flush_tlb_range_psize(struct mm_struct *mm, |
| +static void __radix__flush_tlb_range_psize(struct mm_struct *mm, |
| unsigned long start, unsigned long end, |
| int psize, bool also_pwc) |
| { |
| -- |
| 2.30.2 |
| |