| From 4a27ab6c2231801b27eaee52ee4d38f3e77a3434 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Wed, 26 Jan 2022 15:55:46 +0100 |
| Subject: clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568 |
| |
| From: Sascha Hauer <s.hauer@pengutronix.de> |
| |
| [ Upstream commit ff3187eabb5ce478d15b6ed62eb286756adefac3 ] |
| |
| The pixel clocks dclk_vop[012] can be clocked from hpll, vpll, gpll or |
| cpll. gpll and cpll also drive many other clocks, so changing the |
| dclk_vop[012] clocks could change these other clocks as well. Drop |
| CLK_SET_RATE_PARENT to fix that. With this change the VOP2 driver can |
| only adjust the pixel clocks with the divider between the PLL and the |
| dclk_vop[012] which means the user may have to adjust the PLL clock to a |
| suitable rate using the assigned-clock-rate device tree property. |
| |
| Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> |
| Link: https://lore.kernel.org/r/20220126145549.617165-25-s.hauer@pengutronix.de |
| Signed-off-by: Heiko Stuebner <heiko@sntech.de> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/clk/rockchip/clk-rk3568.c | 6 +++--- |
| 1 file changed, 3 insertions(+), 3 deletions(-) |
| |
| diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c |
| index 69a9e8069a48..604a367bc498 100644 |
| --- a/drivers/clk/rockchip/clk-rk3568.c |
| +++ b/drivers/clk/rockchip/clk-rk3568.c |
| @@ -1038,13 +1038,13 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = { |
| RK3568_CLKGATE_CON(20), 8, GFLAGS), |
| GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0, |
| RK3568_CLKGATE_CON(20), 9, GFLAGS), |
| - COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
| + COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, |
| RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS, |
| RK3568_CLKGATE_CON(20), 10, GFLAGS), |
| - COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, |
| + COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, |
| RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS, |
| RK3568_CLKGATE_CON(20), 11, GFLAGS), |
| - COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0, |
| + COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT, |
| RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS, |
| RK3568_CLKGATE_CON(20), 12, GFLAGS), |
| GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0, |
| -- |
| 2.35.1 |
| |