| From 02fc996d5098f4c3f65bdf6cdb6b28e3f29ba789 Mon Sep 17 00:00:00 2001 |
| From: Emily Deng <Emily.Deng@amd.com> |
| Date: Mon, 21 Mar 2022 16:25:24 +0800 |
| Subject: drm/amdgpu/vcn: Fix the register setting for vcn1 |
| |
| From: Emily Deng <Emily.Deng@amd.com> |
| |
| commit 02fc996d5098f4c3f65bdf6cdb6b28e3f29ba789 upstream. |
| |
| Correct the code error for setting register UVD_GFX10_ADDR_CONFIG. |
| Need to use inst_idx, or it only will set VCN0. |
| |
| Signed-off-by: Emily Deng <Emily.Deng@amd.com> |
| Reviewed-by: James Zhu <James.Zhu@amd.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c |
| +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c |
| @@ -569,8 +569,8 @@ static void vcn_v3_0_mc_resume_dpg_mode( |
| AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect); |
| |
| /* VCN global tiling registers */ |
| - WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET( |
| - UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); |
| + WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET( |
| + UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); |
| } |
| |
| static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst) |
