| From e2932d1f6f055b2af2114c7e64a26dc1b5593d0c Mon Sep 17 00:00:00 2001 |
| From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> |
| Date: Thu, 14 Apr 2022 15:58:13 +0530 |
| Subject: EDAC/synopsys: Read the error count from the correct register |
| |
| From: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> |
| |
| commit e2932d1f6f055b2af2114c7e64a26dc1b5593d0c upstream. |
| |
| Currently, the error count is read wrongly from the status register. Read |
| the count from the proper error count register (ERRCNT). |
| |
| [ bp: Massage. ] |
| |
| Fixes: b500b4a029d5 ("EDAC, synopsys: Add ECC support for ZynqMP DDR controller") |
| Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> |
| Signed-off-by: Borislav Petkov <bp@suse.de> |
| Acked-by: Michal Simek <michal.simek@xilinx.com> |
| Cc: <stable@vger.kernel.org> |
| Link: https://lore.kernel.org/r/20220414102813.4468-1-shubhrajyoti.datta@xilinx.com |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| drivers/edac/synopsys_edac.c | 16 +++++++++++----- |
| 1 file changed, 11 insertions(+), 5 deletions(-) |
| |
| --- a/drivers/edac/synopsys_edac.c |
| +++ b/drivers/edac/synopsys_edac.c |
| @@ -163,6 +163,11 @@ |
| #define ECC_STAT_CECNT_SHIFT 8 |
| #define ECC_STAT_BITNUM_MASK 0x7F |
| |
| +/* ECC error count register definitions */ |
| +#define ECC_ERRCNT_UECNT_MASK 0xFFFF0000 |
| +#define ECC_ERRCNT_UECNT_SHIFT 16 |
| +#define ECC_ERRCNT_CECNT_MASK 0xFFFF |
| + |
| /* DDR QOS Interrupt register definitions */ |
| #define DDR_QOS_IRQ_STAT_OFST 0x20200 |
| #define DDR_QOSUE_MASK 0x4 |
| @@ -418,15 +423,16 @@ static int zynqmp_get_error_info(struct |
| base = priv->baseaddr; |
| p = &priv->stat; |
| |
| + regval = readl(base + ECC_ERRCNT_OFST); |
| + p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; |
| + p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; |
| + if (!p->ce_cnt) |
| + goto ue_err; |
| + |
| regval = readl(base + ECC_STAT_OFST); |
| if (!regval) |
| return 1; |
| |
| - p->ce_cnt = (regval & ECC_STAT_CECNT_MASK) >> ECC_STAT_CECNT_SHIFT; |
| - p->ue_cnt = (regval & ECC_STAT_UECNT_MASK) >> ECC_STAT_UECNT_SHIFT; |
| - if (!p->ce_cnt) |
| - goto ue_err; |
| - |
| p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); |
| |
| regval = readl(base + ECC_CEADDR0_OFST); |