| From 839769c35477d4acc2369e45000ca7b0b6af39a7 Mon Sep 17 00:00:00 2001 |
| From: Max Filippov <jcmvbkbc@gmail.com> |
| Date: Wed, 13 Apr 2022 22:44:36 -0700 |
| Subject: xtensa: fix a7 clobbering in coprocessor context load/store |
| |
| From: Max Filippov <jcmvbkbc@gmail.com> |
| |
| commit 839769c35477d4acc2369e45000ca7b0b6af39a7 upstream. |
| |
| Fast coprocessor exception handler saves a3..a6, but coprocessor context |
| load/store code uses a4..a7 as temporaries, potentially clobbering a7. |
| 'Potentially' because coprocessor state load/store macros may not use |
| all four temporary registers (and neither FPU nor HiFi macros do). |
| Use a3..a6 as intended. |
| |
| Cc: stable@vger.kernel.org |
| Fixes: c658eac628aa ("[XTENSA] Add support for configurable registers and coprocessors") |
| Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| --- |
| arch/xtensa/kernel/coprocessor.S | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| --- a/arch/xtensa/kernel/coprocessor.S |
| +++ b/arch/xtensa/kernel/coprocessor.S |
| @@ -37,7 +37,7 @@ |
| .if XTENSA_HAVE_COPROCESSOR(x); \ |
| .align 4; \ |
| .Lsave_cp_regs_cp##x: \ |
| - xchal_cp##x##_store a2 a4 a5 a6 a7; \ |
| + xchal_cp##x##_store a2 a3 a4 a5 a6; \ |
| jx a0; \ |
| .endif |
| |
| @@ -54,7 +54,7 @@ |
| .if XTENSA_HAVE_COPROCESSOR(x); \ |
| .align 4; \ |
| .Lload_cp_regs_cp##x: \ |
| - xchal_cp##x##_load a2 a4 a5 a6 a7; \ |
| + xchal_cp##x##_load a2 a3 a4 a5 a6; \ |
| jx a0; \ |
| .endif |
| |
