| From 78722d37b2b4cf9178295e2aa5510880e6135fd7 Mon Sep 17 00:00:00 2001 |
| From: Suman Anna <s-anna@ti.com> |
| Date: Tue, 11 Feb 2020 09:51:03 -0600 |
| Subject: ARM: dts: dra7xx-clocks: Fixup IPU1 mux clock parent source |
| |
| From: Suman Anna <s-anna@ti.com> |
| |
| commit 78722d37b2b4cf9178295e2aa5510880e6135fd7 upstream. |
| |
| The IPU1 functional clock is the output of a mux clock (represented |
| by ipu1_gfclk_mux previously) and the clock source for this has been |
| updated to be sourced from dpll_core_h22x2_ck in commit 39879c7d963e |
| ("ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL"). |
| ipu1_gfclk_mux is an obsolete clock now with the clkctrl conversion, |
| and this clock source parenting is lost during the new clkctrl layout |
| conversion. |
| |
| Remove this stale clock and fix up the clock source for this mux |
| clock using the latest equivalent clkctrl clock. This restores the |
| previous logic and ensures that the IPU1 continues to run at the |
| same frequency of IPU2 and independent of the ABE DPLL. |
| |
| Fixes: b5f8ffbb6fad ("ARM: dts: dra7: convert to use new clkctrl layout") |
| Signed-off-by: Suman Anna <s-anna@ti.com> |
| Signed-off-by: Tony Lindgren <tony@atomide.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/arm/boot/dts/dra7xx-clocks.dtsi | 12 ++---------- |
| 1 file changed, 2 insertions(+), 10 deletions(-) |
| |
| --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi |
| +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi |
| @@ -796,16 +796,6 @@ |
| clock-div = <1>; |
| }; |
| |
| - ipu1_gfclk_mux: ipu1_gfclk_mux@520 { |
| - #clock-cells = <0>; |
| - compatible = "ti,mux-clock"; |
| - clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; |
| - ti,bit-shift = <24>; |
| - reg = <0x0520>; |
| - assigned-clocks = <&ipu1_gfclk_mux>; |
| - assigned-clock-parents = <&dpll_core_h22x2_ck>; |
| - }; |
| - |
| dummy_ck: dummy_ck { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| @@ -1564,6 +1554,8 @@ |
| compatible = "ti,clkctrl"; |
| reg = <0x20 0x4>; |
| #clock-cells = <2>; |
| + assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>; |
| + assigned-clock-parents = <&dpll_core_h22x2_ck>; |
| }; |
| |
| ipu_clkctrl: ipu-clkctrl@50 { |