| From ad9cc9e508e5713ee4c4f3288b78e22265d4d8e8 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Wed, 15 Apr 2020 16:34:34 -0700 |
| Subject: drm/i915/tgl: TBT AUX should use TC power well ops |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| From: Matt Roper <matthew.d.roper@intel.com> |
| |
| [ Upstream commit 335f62e7606a7921775d7cc73f0ad8ffd899bc22 ] |
| |
| As on ICL, we want to use the Type-C aux handlers for the TBT aux wells |
| to ensure the DP_AUX_CH_CTL_TBT_IO flag is set properly. |
| |
| Fixes: 656409bbaf87 ("drm/i915/tgl: Add power well support") |
| Cc: José Roberto de Souza <jose.souza@intel.com> |
| Cc: Imre Deak <imre.deak@intel.com> |
| Signed-off-by: Matt Roper <matthew.d.roper@intel.com> |
| Link: https://patchwork.freedesktop.org/patch/msgid/20200415233435.3064257-1-matthew.d.roper@intel.com |
| Reviewed-by: José Roberto de Souza <jose.souza@intel.com> |
| (cherry picked from commit 3cbdb97564a39020262e62b655e788b63cf426cb) |
| Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++++++------ |
| 1 file changed, 6 insertions(+), 6 deletions(-) |
| |
| diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c |
| index 46c40db992dd7..5895b8c7662e3 100644 |
| --- a/drivers/gpu/drm/i915/display/intel_display_power.c |
| +++ b/drivers/gpu/drm/i915/display/intel_display_power.c |
| @@ -4068,7 +4068,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { |
| { |
| .name = "AUX D TBT1", |
| .domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS, |
| - .ops = &hsw_power_well_ops, |
| + .ops = &icl_tc_phy_aux_power_well_ops, |
| .id = DISP_PW_ID_NONE, |
| { |
| .hsw.regs = &icl_aux_power_well_regs, |
| @@ -4079,7 +4079,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { |
| { |
| .name = "AUX E TBT2", |
| .domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS, |
| - .ops = &hsw_power_well_ops, |
| + .ops = &icl_tc_phy_aux_power_well_ops, |
| .id = DISP_PW_ID_NONE, |
| { |
| .hsw.regs = &icl_aux_power_well_regs, |
| @@ -4090,7 +4090,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { |
| { |
| .name = "AUX F TBT3", |
| .domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS, |
| - .ops = &hsw_power_well_ops, |
| + .ops = &icl_tc_phy_aux_power_well_ops, |
| .id = DISP_PW_ID_NONE, |
| { |
| .hsw.regs = &icl_aux_power_well_regs, |
| @@ -4101,7 +4101,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { |
| { |
| .name = "AUX G TBT4", |
| .domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS, |
| - .ops = &hsw_power_well_ops, |
| + .ops = &icl_tc_phy_aux_power_well_ops, |
| .id = DISP_PW_ID_NONE, |
| { |
| .hsw.regs = &icl_aux_power_well_regs, |
| @@ -4112,7 +4112,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { |
| { |
| .name = "AUX H TBT5", |
| .domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS, |
| - .ops = &hsw_power_well_ops, |
| + .ops = &icl_tc_phy_aux_power_well_ops, |
| .id = DISP_PW_ID_NONE, |
| { |
| .hsw.regs = &icl_aux_power_well_regs, |
| @@ -4123,7 +4123,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { |
| { |
| .name = "AUX I TBT6", |
| .domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS, |
| - .ops = &hsw_power_well_ops, |
| + .ops = &icl_tc_phy_aux_power_well_ops, |
| .id = DISP_PW_ID_NONE, |
| { |
| .hsw.regs = &icl_aux_power_well_regs, |
| -- |
| 2.20.1 |
| |
