| From 48084c3595cb7429f6ba734cfea1313573b9a7fa Mon Sep 17 00:00:00 2001 |
| From: Kefeng Wang <wangkefeng.wang@huawei.com> |
| Date: Thu, 7 May 2020 23:04:45 +0800 |
| Subject: riscv: perf: RISCV_BASE_PMU should be independent |
| |
| From: Kefeng Wang <wangkefeng.wang@huawei.com> |
| |
| commit 48084c3595cb7429f6ba734cfea1313573b9a7fa upstream. |
| |
| Selecting PERF_EVENTS without selecting RISCV_BASE_PMU results in a build |
| error. |
| |
| Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com> |
| [Palmer: commit text] |
| Fixes: 178e9fc47aae("perf: riscv: preliminary RISC-V support") |
| Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/riscv/include/asm/perf_event.h | 8 ++------ |
| arch/riscv/kernel/Makefile | 2 +- |
| 2 files changed, 3 insertions(+), 7 deletions(-) |
| |
| --- a/arch/riscv/include/asm/perf_event.h |
| +++ b/arch/riscv/include/asm/perf_event.h |
| @@ -12,19 +12,14 @@ |
| #include <linux/ptrace.h> |
| #include <linux/interrupt.h> |
| |
| +#ifdef CONFIG_RISCV_BASE_PMU |
| #define RISCV_BASE_COUNTERS 2 |
| |
| /* |
| * The RISCV_MAX_COUNTERS parameter should be specified. |
| */ |
| |
| -#ifdef CONFIG_RISCV_BASE_PMU |
| #define RISCV_MAX_COUNTERS 2 |
| -#endif |
| - |
| -#ifndef RISCV_MAX_COUNTERS |
| -#error "Please provide a valid RISCV_MAX_COUNTERS for the PMU." |
| -#endif |
| |
| /* |
| * These are the indexes of bits in counteren register *minus* 1, |
| @@ -82,6 +77,7 @@ struct riscv_pmu { |
| int irq; |
| }; |
| |
| +#endif |
| #ifdef CONFIG_PERF_EVENTS |
| #define perf_arch_bpf_user_pt_regs(regs) (struct user_regs_struct *)regs |
| #endif |
| --- a/arch/riscv/kernel/Makefile |
| +++ b/arch/riscv/kernel/Makefile |
| @@ -38,7 +38,7 @@ obj-$(CONFIG_MODULE_SECTIONS) += module- |
| obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o |
| obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o |
| |
| -obj-$(CONFIG_PERF_EVENTS) += perf_event.o |
| +obj-$(CONFIG_RISCV_BASE_PMU) += perf_event.o |
| obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o |
| obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o |
| obj-$(CONFIG_RISCV_SBI) += sbi.o |