| From 29a541f6c1f6e4a85628bb86071b9e72c9f8be2c Mon Sep 17 00:00:00 2001 |
| From: Will Deacon <will.deacon@arm.com> |
| Date: Mon, 3 Oct 2011 18:30:53 +0100 |
| Subject: ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9 |
| |
| From: Will Deacon <will.deacon@arm.com> |
| |
| commit 29a541f6c1f6e4a85628bb86071b9e72c9f8be2c upstream. |
| |
| Using COHERENT_LINE_{MISS,HIT} for cache misses and references |
| respectively is completely wrong. Instead, use the L1D events which |
| are a better and more useful approximation despite ignoring instruction |
| traffic. |
| |
| Reported-by: Alasdair Grant <alasdair.grant@arm.com> |
| Reported-by: Matt Horsnell <matt.horsnell@arm.com> |
| Reported-by: Michael Williams <michael.williams@arm.com> |
| Cc: Jean Pihet <j-pihet@ti.com> |
| Signed-off-by: Will Deacon <will.deacon@arm.com> |
| Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> |
| |
| --- |
| arch/arm/kernel/perf_event_v7.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| --- a/arch/arm/kernel/perf_event_v7.c |
| +++ b/arch/arm/kernel/perf_event_v7.c |
| @@ -264,8 +264,8 @@ static const unsigned armv7_a9_perf_map[ |
| [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, |
| [PERF_COUNT_HW_INSTRUCTIONS] = |
| ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE, |
| - [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT, |
| - [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS, |
| + [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_DCACHE_ACCESS, |
| + [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_DCACHE_REFILL, |
| [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, |
| [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, |
| [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, |
