| From 15ebb05248d025534773c9ef64915bd888f04e4b Mon Sep 17 00:00:00 2001 |
| From: Thomas Gleixner <tglx@linutronix.de> |
| Date: Thu, 19 Jun 2014 21:52:23 +0000 |
| Subject: clk: spear3xx: Use proper control register offset |
| |
| From: Thomas Gleixner <tglx@linutronix.de> |
| |
| commit 15ebb05248d025534773c9ef64915bd888f04e4b upstream. |
| |
| The control register is at offset 0x10, not 0x0. This is wreckaged |
| since commit 5df33a62c (SPEAr: Switch to common clock framework). |
| |
| Signed-off-by: Thomas Gleixner <tglx@linutronix.de> |
| Acked-by: Viresh Kumar <viresh.kumar@linaro.org> |
| Signed-off-by: Mike Turquette <mturquette@linaro.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/clk/spear/spear3xx_clock.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/drivers/clk/spear/spear3xx_clock.c |
| +++ b/drivers/clk/spear/spear3xx_clock.c |
| @@ -211,7 +211,7 @@ static inline void spear310_clk_init(voi |
| /* array of all spear 320 clock lookups */ |
| #ifdef CONFIG_MACH_SPEAR320 |
| |
| -#define SPEAR320_CONTROL_REG (soc_config_base + 0x0000) |
| +#define SPEAR320_CONTROL_REG (soc_config_base + 0x0010) |
| #define SPEAR320_EXT_CTRL_REG (soc_config_base + 0x0018) |
| |
| #define SPEAR320_UARTX_PCLK_MASK 0x1 |
