| From 3ad50d2f4c94c94b495d711e9fb3c00e29e95a2a Mon Sep 17 00:00:00 2001 |
| From: Anson Huang <anson.huang@nxp.com> |
| Date: Fri, 30 Nov 2018 07:23:47 +0000 |
| Subject: clk: imx6sl: ensure MMDC CH0 handshake is bypassed |
| |
| [ Upstream commit 0efcc2c0fd2001a83240a8c3d71f67770484917e ] |
| |
| Same as other i.MX6 SoCs, ensure unused MMDC channel's |
| handshake is bypassed, this is to make sure no request |
| signal will be generated when periphe_clk_sel is changed |
| or SRC warm reset is triggered. |
| |
| Signed-off-by: Anson Huang <Anson.Huang@nxp.com> |
| Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| drivers/clk/imx/clk-imx6sl.c | 6 ++++++ |
| 1 file changed, 6 insertions(+) |
| |
| diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c |
| index 9642cdf0fb88..c264a744fae8 100644 |
| --- a/drivers/clk/imx/clk-imx6sl.c |
| +++ b/drivers/clk/imx/clk-imx6sl.c |
| @@ -17,6 +17,8 @@ |
| |
| #include "clk.h" |
| |
| +#define CCDR 0x4 |
| +#define BM_CCM_CCDR_MMDC_CH0_MASK (1 << 17) |
| #define CCSR 0xc |
| #define BM_CCSR_PLL1_SW_CLK_SEL (1 << 2) |
| #define CACRR 0x10 |
| @@ -414,6 +416,10 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) |
| clks[IMX6SL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); |
| clks[IMX6SL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); |
| |
| + /* Ensure the MMDC CH0 handshake is bypassed */ |
| + writel_relaxed(readl_relaxed(base + CCDR) | |
| + BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR); |
| + |
| imx_check_clocks(clks, ARRAY_SIZE(clks)); |
| |
| clk_data.clks = clks; |
| -- |
| 2.19.1 |
| |