| From a6aa36108c8a9839a5ae57cc165492693dcee47d Mon Sep 17 00:00:00 2001 |
| From: Stefan Roese <sr@denx.de> |
| Date: Mon, 17 Dec 2018 10:47:48 +0100 |
| Subject: MIPS: ralink: Select CONFIG_CPU_MIPSR2_IRQ_VI on MT7620/8 |
| |
| [ Upstream commit 0b15394475e3bcaf35ca4bf22fc55d56df67224e ] |
| |
| Testing has shown, that when using mainline U-Boot on MT7688 based |
| boards, the system may hang or crash while mounting the root-fs. The |
| main issue here is that mainline U-Boot configures EBase to a value |
| near the end of system memory. And with CONFIG_CPU_MIPSR2_IRQ_VI |
| disabled, trap_init() will not allocate a new area to place the |
| exception handler. The original value will be used and the handler |
| will be copied to this location, which might already be used by some |
| userspace application. |
| |
| The MT7688 supports VI - its config3 register is 0x00002420, so VInt |
| (Bit 5) is set. But without setting CONFIG_CPU_MIPSR2_IRQ_VI this |
| bit will not be evaluated to result in "cpu_has_vi" being set. This |
| patch now selects CONFIG_CPU_MIPSR2_IRQ_VI on MT7620/8 which results |
| trap_init() to allocate some memory for the exception handler. |
| |
| Please note that this issue was not seen with the Mediatek U-Boot |
| version, as it does not touch EBase (stays at default of 0x8000.0000). |
| This is strictly also not correct as the kernel (_text) resides |
| here. |
| |
| Signed-off-by: Stefan Roese <sr@denx.de> |
| [paul.burton@mips.com: s/beeing/being/] |
| Signed-off-by: Paul Burton <paul.burton@mips.com> |
| Cc: John Crispin <blogic@openwrt.org> |
| Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
| Cc: Ralf Baechle <ralf@linux-mips.org> |
| Cc: linux-mips@linux-mips.org |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| arch/mips/ralink/Kconfig | 1 + |
| 1 file changed, 1 insertion(+) |
| |
| diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig |
| index f26736b7080b..fae36f0371d3 100644 |
| --- a/arch/mips/ralink/Kconfig |
| +++ b/arch/mips/ralink/Kconfig |
| @@ -39,6 +39,7 @@ choice |
| |
| config SOC_MT7620 |
| bool "MT7620/8" |
| + select CPU_MIPSR2_IRQ_VI |
| select HW_HAS_PCI |
| |
| config SOC_MT7621 |
| -- |
| 2.19.1 |
| |