| From 3fe3331bb285700ab2253dbb07f8e478fcea2f1b Mon Sep 17 00:00:00 2001 |
| From: Kim Phillips <kim.phillips@amd.com> |
| Date: Thu, 21 Mar 2019 21:15:22 +0000 |
| Subject: perf/x86/amd: Add event map for AMD Family 17h |
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| |
| From: Kim Phillips <kim.phillips@amd.com> |
| |
| commit 3fe3331bb285700ab2253dbb07f8e478fcea2f1b upstream. |
| |
| Family 17h differs from prior families by: |
| |
| - Does not support an L2 cache miss event |
| - It has re-enumerated PMC counters for: |
| - L2 cache references |
| - front & back end stalled cycles |
| |
| So we add a new amd_f17h_perfmon_event_map[] so that the generic |
| perf event names will resolve to the correct h/w events on |
| family 17h and above processors. |
| |
| Reference sections 2.1.13.3.3 (stalls) and 2.1.13.3.6 (L2): |
| |
| https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf |
| |
| Signed-off-by: Kim Phillips <kim.phillips@amd.com> |
| Cc: <stable@vger.kernel.org> # v4.9+ |
| Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> |
| Cc: Arnaldo Carvalho de Melo <acme@kernel.org> |
| Cc: Borislav Petkov <bp@alien8.de> |
| Cc: H. Peter Anvin <hpa@zytor.com> |
| Cc: Janakarajan Natarajan <Janakarajan.Natarajan@amd.com> |
| Cc: Jiri Olsa <jolsa@redhat.com> |
| Cc: Linus Torvalds <torvalds@linux-foundation.org> |
| Cc: Martin Liลกka <mliska@suse.cz> |
| Cc: Namhyung Kim <namhyung@kernel.org> |
| Cc: Peter Zijlstra <peterz@infradead.org> |
| Cc: Pu Wen <puwen@hygon.cn> |
| Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> |
| Cc: Thomas Gleixner <tglx@linutronix.de> |
| Cc: linux-kernel@vger.kernel.org |
| Fixes: e40ed1542dd7 ("perf/x86: Add perf support for AMD family-17h processors") |
| [ Improved the formatting a bit. ] |
| Signed-off-by: Ingo Molnar <mingo@kernel.org> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| arch/x86/events/amd/core.c | 35 ++++++++++++++++++++++++++--------- |
| 1 file changed, 26 insertions(+), 9 deletions(-) |
| |
| --- a/arch/x86/events/amd/core.c |
| +++ b/arch/x86/events/amd/core.c |
| @@ -113,22 +113,39 @@ static __initconst const u64 amd_hw_cach |
| }; |
| |
| /* |
| - * AMD Performance Monitor K7 and later. |
| + * AMD Performance Monitor K7 and later, up to and including Family 16h: |
| */ |
| static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] = |
| { |
| - [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, |
| - [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, |
| - [PERF_COUNT_HW_CACHE_REFERENCES] = 0x077d, |
| - [PERF_COUNT_HW_CACHE_MISSES] = 0x077e, |
| - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2, |
| - [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, |
| - [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" event */ |
| - [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x00d1, /* "Dispatch stalls" event */ |
| + [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, |
| + [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, |
| + [PERF_COUNT_HW_CACHE_REFERENCES] = 0x077d, |
| + [PERF_COUNT_HW_CACHE_MISSES] = 0x077e, |
| + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2, |
| + [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, |
| + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" event */ |
| + [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x00d1, /* "Dispatch stalls" event */ |
| +}; |
| + |
| +/* |
| + * AMD Performance Monitor Family 17h and later: |
| + */ |
| +static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] = |
| +{ |
| + [PERF_COUNT_HW_CPU_CYCLES] = 0x0076, |
| + [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0, |
| + [PERF_COUNT_HW_CACHE_REFERENCES] = 0xff60, |
| + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c2, |
| + [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, |
| + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x0287, |
| + [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x0187, |
| }; |
| |
| static u64 amd_pmu_event_map(int hw_event) |
| { |
| + if (boot_cpu_data.x86 >= 0x17) |
| + return amd_f17h_perfmon_event_map[hw_event]; |
| + |
| return amd_perfmon_event_map[hw_event]; |
| } |
| |