| From ee66c2f1dce5796914d03764f2b61d63ffe3c586 Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Thu, 3 Oct 2019 12:12:08 +0100 |
| Subject: arm64: cpufeature: Effectively expose FRINT capability to userspace |
| |
| From: Julien Grall <julien.grall@arm.com> |
| |
| [ Upstream commit 7230f7e99fecc684180322b056fad3853d1029d3 ] |
| |
| The HWCAP framework will detect a new capability based on the sanitized |
| version of the ID registers. |
| |
| Sanitization is based on a whitelist, so any field not described will end |
| up to be zeroed. |
| |
| At the moment, ID_AA64ISAR1_EL1.FRINTTS is not described in |
| ftr_id_aa64isar1. This means the field will be zeroed and therefore the |
| userspace will not be able to see the HWCAP even if the hardware |
| supports the feature. |
| |
| This can be fixed by describing the field in ftr_id_aa64isar1. |
| |
| Fixes: ca9503fc9e98 ("arm64: Expose FRINT capabilities to userspace") |
| Signed-off-by: Julien Grall <julien.grall@arm.com> |
| Cc: mark.brown@arm.com |
| Signed-off-by: Will Deacon <will@kernel.org> |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| arch/arm64/kernel/cpufeature.c | 1 + |
| 1 file changed, 1 insertion(+) |
| |
| diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c |
| index 9323bcc40a58a..cabebf1a79768 100644 |
| --- a/arch/arm64/kernel/cpufeature.c |
| +++ b/arch/arm64/kernel/cpufeature.c |
| @@ -136,6 +136,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { |
| |
| static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { |
| ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0), |
| + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0), |
| ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), |
| FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0), |
| ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), |
| -- |
| 2.20.1 |
| |
