| From f52ebe1f888dfae68d7cffabf5ac898f8cb64fb3 Mon Sep 17 00:00:00 2001 |
| From: "Tianci.Yin" <tianci.yin@amd.com> |
| Date: Thu, 24 Oct 2019 18:03:17 +0800 |
| Subject: drm/amdgpu/gfx10: update gfx golden settings |
| |
| From: Tianci.Yin <tianci.yin@amd.com> |
| |
| commit f52ebe1f888dfae68d7cffabf5ac898f8cb64fb3 upstream. |
| |
| update registers: mmCGTT_SPI_CLK_CTRL |
| |
| Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> |
| Signed-off-by: Tianci.Yin <tianci.yin@amd.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |
| +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c |
| @@ -67,7 +67,7 @@ static const struct soc15_reg_golden gol |
| { |
| SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100), |
| - SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xc0000000, 0xc0000100), |
| + SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100), |
| SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100), |
