| From 30ef5c7eaba0ddafc6c23eca65ebe52169dfcc60 Mon Sep 17 00:00:00 2001 |
| From: Alex Deucher <alexander.deucher@amd.com> |
| Date: Tue, 29 Oct 2019 17:14:15 -0400 |
| Subject: drm/amdgpu/gmc10: properly set BANK_SELECT and FRAGMENT_SIZE |
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| |
| From: Alex Deucher <alexander.deucher@amd.com> |
| |
| commit 30ef5c7eaba0ddafc6c23eca65ebe52169dfcc60 upstream. |
| |
| These were not aligned for optimal performance for GPUVM. |
| |
| Acked-by: Christian Kรถnig <christian.koenig@amd.com> |
| Reviewed-by: Tianci Yin <tianci.yin@amd.com> |
| Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
| Cc: stable@vger.kernel.org |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| |
| --- |
| drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c | 9 +++++++++ |
| drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 9 +++++++++ |
| 2 files changed, 18 insertions(+) |
| |
| --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c |
| +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c |
| @@ -151,6 +151,15 @@ static void gfxhub_v2_0_init_cache_regs( |
| WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, tmp); |
| |
| tmp = mmGCVM_L2_CNTL3_DEFAULT; |
| + if (adev->gmc.translate_further) { |
| + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12); |
| + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, |
| + L2_CACHE_BIGK_FRAGMENT_SIZE, 9); |
| + } else { |
| + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9); |
| + tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, |
| + L2_CACHE_BIGK_FRAGMENT_SIZE, 6); |
| + } |
| WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL3, tmp); |
| |
| tmp = mmGCVM_L2_CNTL4_DEFAULT; |
| --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c |
| +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c |
| @@ -137,6 +137,15 @@ static void mmhub_v2_0_init_cache_regs(s |
| WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp); |
| |
| tmp = mmMMVM_L2_CNTL3_DEFAULT; |
| + if (adev->gmc.translate_further) { |
| + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12); |
| + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, |
| + L2_CACHE_BIGK_FRAGMENT_SIZE, 9); |
| + } else { |
| + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9); |
| + tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, |
| + L2_CACHE_BIGK_FRAGMENT_SIZE, 6); |
| + } |
| WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp); |
| |
| tmp = mmMMVM_L2_CNTL4_DEFAULT; |