| From 06acb472effb32b90a3dba3e788effac89e2eb1e Mon Sep 17 00:00:00 2001 |
| From: Sasha Levin <sashal@kernel.org> |
| Date: Tue, 28 Jan 2020 10:31:18 -0800 |
| Subject: perf/x86/cstate: Add Tremont support |
| |
| From: Kan Liang <kan.liang@linux.intel.com> |
| |
| [ Upstream commit ecf71fbccb9ac5cb964eb7de59bb9da3755b7885 ] |
| |
| Tremont is Intel's successor to Goldmont Plus. From the perspective of |
| Intel cstate residency counters, there is nothing changed compared with |
| Goldmont Plus and Goldmont. |
| |
| Share glm_cstates with Goldmont Plus and Goldmont. |
| Update the comments for Tremont. |
| |
| Signed-off-by: Kan Liang <kan.liang@linux.intel.com> |
| Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> |
| Signed-off-by: Ingo Molnar <mingo@kernel.org> |
| Reviewed-by: Andi Kleen <ak@linux.intel.com> |
| Link: https://lkml.kernel.org/r/1580236279-35492-2-git-send-email-kan.liang@linux.intel.com |
| Signed-off-by: Sasha Levin <sashal@kernel.org> |
| --- |
| arch/x86/events/intel/cstate.c | 22 +++++++++++++--------- |
| 1 file changed, 13 insertions(+), 9 deletions(-) |
| |
| diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c |
| index e1daf4151e116..4814c964692cb 100644 |
| --- a/arch/x86/events/intel/cstate.c |
| +++ b/arch/x86/events/intel/cstate.c |
| @@ -40,17 +40,18 @@ |
| * Model specific counters: |
| * MSR_CORE_C1_RES: CORE C1 Residency Counter |
| * perf code: 0x00 |
| - * Available model: SLM,AMT,GLM,CNL |
| + * Available model: SLM,AMT,GLM,CNL,TNT |
| * Scope: Core (each processor core has a MSR) |
| * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter |
| * perf code: 0x01 |
| * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM, |
| - * CNL,KBL,CML |
| + * CNL,KBL,CML,TNT |
| * Scope: Core |
| * MSR_CORE_C6_RESIDENCY: CORE C6 Residency Counter |
| * perf code: 0x02 |
| * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, |
| - * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL |
| + * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL, |
| + * TNT |
| * Scope: Core |
| * MSR_CORE_C7_RESIDENCY: CORE C7 Residency Counter |
| * perf code: 0x03 |
| @@ -60,17 +61,18 @@ |
| * MSR_PKG_C2_RESIDENCY: Package C2 Residency Counter. |
| * perf code: 0x00 |
| * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, |
| - * KBL,CML,ICL,TGL |
| + * KBL,CML,ICL,TGL,TNT |
| * Scope: Package (physical package) |
| * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. |
| * perf code: 0x01 |
| * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,KNL, |
| - * GLM,CNL,KBL,CML,ICL,TGL |
| + * GLM,CNL,KBL,CML,ICL,TGL,TNT |
| * Scope: Package (physical package) |
| * MSR_PKG_C6_RESIDENCY: Package C6 Residency Counter. |
| * perf code: 0x02 |
| - * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW |
| - * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL |
| + * Available model: SLM,AMT,NHM,WSM,SNB,IVB,HSW,BDW, |
| + * SKL,KNL,GLM,CNL,KBL,CML,ICL,TGL, |
| + * TNT |
| * Scope: Package (physical package) |
| * MSR_PKG_C7_RESIDENCY: Package C7 Residency Counter. |
| * perf code: 0x03 |
| @@ -87,7 +89,8 @@ |
| * Scope: Package (physical package) |
| * MSR_PKG_C10_RESIDENCY: Package C10 Residency Counter. |
| * perf code: 0x06 |
| - * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL |
| + * Available model: HSW ULT,KBL,GLM,CNL,CML,ICL,TGL, |
| + * TNT |
| * Scope: Package (physical package) |
| * |
| */ |
| @@ -640,8 +643,9 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { |
| |
| X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT, glm_cstates), |
| X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_D, glm_cstates), |
| - |
| X86_CSTATES_MODEL(INTEL_FAM6_ATOM_GOLDMONT_PLUS, glm_cstates), |
| + X86_CSTATES_MODEL(INTEL_FAM6_ATOM_TREMONT_D, glm_cstates), |
| + X86_CSTATES_MODEL(INTEL_FAM6_ATOM_TREMONT, glm_cstates), |
| |
| X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE_L, icl_cstates), |
| X86_CSTATES_MODEL(INTEL_FAM6_ICELAKE, icl_cstates), |
| -- |
| 2.20.1 |
| |