| /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ |
| /* |
| * This header provides clock numbers for the ingenic,jz4755-cgu DT binding. |
| */ |
| |
| #ifndef __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ |
| #define __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ |
| |
| #define JZ4755_CLK_EXT 0 |
| #define JZ4755_CLK_OSC32K 1 |
| #define JZ4755_CLK_PLL 2 |
| #define JZ4755_CLK_PLL_HALF 3 |
| #define JZ4755_CLK_EXT_HALF 4 |
| #define JZ4755_CLK_CCLK 5 |
| #define JZ4755_CLK_H0CLK 6 |
| #define JZ4755_CLK_PCLK 7 |
| #define JZ4755_CLK_MCLK 8 |
| #define JZ4755_CLK_H1CLK 9 |
| #define JZ4755_CLK_UDC 10 |
| #define JZ4755_CLK_LCD 11 |
| #define JZ4755_CLK_UART0 12 |
| #define JZ4755_CLK_UART1 13 |
| #define JZ4755_CLK_UART2 14 |
| #define JZ4755_CLK_DMA 15 |
| #define JZ4755_CLK_MMC 16 |
| #define JZ4755_CLK_MMC0 17 |
| #define JZ4755_CLK_MMC1 18 |
| #define JZ4755_CLK_EXT512 19 |
| #define JZ4755_CLK_RTC 20 |
| #define JZ4755_CLK_UDC_PHY 21 |
| #define JZ4755_CLK_I2S 22 |
| #define JZ4755_CLK_SPI 23 |
| #define JZ4755_CLK_AIC 24 |
| #define JZ4755_CLK_ADC 25 |
| #define JZ4755_CLK_TCU 26 |
| #define JZ4755_CLK_BCH 27 |
| #define JZ4755_CLK_I2C 28 |
| #define JZ4755_CLK_TVE 29 |
| #define JZ4755_CLK_CIM 30 |
| #define JZ4755_CLK_AUX_CPU 31 |
| #define JZ4755_CLK_AHB1 32 |
| #define JZ4755_CLK_IDCT 33 |
| #define JZ4755_CLK_DB 34 |
| #define JZ4755_CLK_ME 35 |
| #define JZ4755_CLK_MC 36 |
| #define JZ4755_CLK_TSSI 37 |
| #define JZ4755_CLK_IPU 38 |
| |
| #endif /* __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ */ |
